Phase relationship between the sampling clock input(CKP/N) and the internal divider output(DCKOP/N) of LTC2000?

Is there a fixed phase relationship between the sampling clock input(CKP/N) and the internal divider output(DCKOP/N) after each power-up of the LTC2000?

If it is fixed, what is the phase difference?
If it is not fixed, will this clock be used as the reference clock of the FPGA/ASIC to affect the synchronization of the analog output between the multiple LTC2000s?

Thanks!