Is there a fixed phase relationship between the sampling clock input(CKP/N) and the internal divider output(DCKOP/N) after each power-up of the LTC2000?
If it is fixed, what is the phase difference?If it is not fixed, will this clock be used as the reference clock of the FPGA/ASIC to affect the synchronization of the analog output between the multiple LTC2000s?
Sorry, the format is wrong, re-issue it again.
Moved to Precision DAC forum. Clarence.Mayott, can you take a look, please?
On start up DCKOP will be a divided version of the sample clock. The standard startup value is divide by 4. The signals will be in phase, but that isn't critical, the critical spec is DCKIN to sample clock which is controlled in the FPGA.
We have a verilog example on how to align mulitple LTC2000s on our website: https://www.analog.com/media/en/dsp-hardware-software/evaluation-code/ltc2000_align_all_DACs.v