I have been working on AD5065. But I haven't gotten it worked for 2 days. Something is weird.
I attached my schematic. First of all, I have checked all the power and data line connectivity. It looks that everything is ok..
I also attached the Spi communication screenshots. As much as I understand from the datasheet, I put the data on the rising edge of the Sclk and data will be valid for DAC on the falling edge of the Sclk. I also paid attention on the timings, especially the timing for the last falling edge of Slck to rising edge of Sync which is 5 ns in my case. I set Sclk period is 25MHz. I also set Ldac to "0", CLR and PDL pins to "1" as a constant value in software. Because Ldac=0, the outputs should be automatically updated when I set the input register.
For example, I set the input register to generate 2V
for DAC A : "0000 0000 0000 1100 1100 1100 1101 0000"
for DAC B : "0000 0000 0011 1100 1100 1100 1101 0000"
But there is no response. Both channels always have zero volts. I thought there might be a wake-up command. I found power-up command and I applied it at the beginning which is
"0000 0100 0000 0000 0000 0000 0000 1111"
But the outputs still shows zero volt. Am I doing something wrong? Is there any initialization process to get this DAC running?
Any advise would be helpful. Thank you.
Based on your scope shots, it seems that your are not writing 2.0V. The data is interpreted at the falling of SCLK so the data that the AD5065 is receiving is:
"0000 0000 0011 1001 1001 1001 1010 0000", this is equivalent to 1.5V.
Thank you for your help. I tried the power-down modes which are
"0000 0100 0000 0000 0000 0001 0000 1111"
"0000 0100 0000 0000 0000 0010 0000 1111"
"0000 0100 0000 0000 0000 0011 0000 1111"
But nothing changed. I still see zero volts. I tried power-up command after power-down command. But it is still the same.
LDAC, CLR, and PDL are set while FPGA is powering up. So, these pins are set way before the first write operation and stay constant. I never change them.
I also checked SDO pin with the scope. As much as I understand from the datasheet, I should see the previous 32-bit data. But there is no change in SDO, it is always zero volts. I suspected the IC is broken. I replaced it. But it doesn't work, too.
Can you provide scope shots for the power-down sequence?
For the SDO, this is disabled by default, you need to write to the DCEN register first before you could see anything on the SDO pin.
I have attached the screenshots. I zoomed for a better look. There are three power-down modes. Here, I used "1 kΩ to GND"
Yesterday, I had also tried others. I also set Ldac to "0", CLR and PDL pins to "1" as a constant value in software. I never change them. They are set before the first write operation.
On the other hand, Yesterday I had also tried Daisy-Chain Mode, and set the register as
"0000 1000 0000 0000 0000 0000 0000 0010"
But there was no change on SDO pin. It is always zero volts.
You are operating on power down mode if you are setting DB8 and DB8 to "01".
Have you tried using "00"? the DACs should operate normally with this setting.
"0000 0100 0000 0000 0000 0000 0000 1111".
Have you measured at the VREFA and VREFB pins? is the 2.5V present?
For the SDO, did you send another 32 clock cycles after your write sequence? Can you take a scope shot of this as well?