A few questions about this DAC:
1) Based on the timing characteristics of the digital interface for Vdd = 3.3V, it should be feasible to update the LTC2757 at 16.66 MHz. However, if the output settling time specification in the datasheet is 2.1 us, does this mean that I should not being updating any faster than 476 kHz (or 555 kHz if optimizing settling time to 1.8us per Note 7)?
2) Is the settling time dependent on the step size? The datasheet states conditions for a span code = 000, which is 0-5V, but also states for a 10V step. In my experiments on the eval board, the size of the step didn't seem to affect the settling time.
3) I am having trouble understanding the graph of multiplying frequency response vs digital code. Why is there an individual line per bit rather than a single line for attenuation vs frequency?
What are the frequencies you are trying to generate? What is your sample rate?
Our application will primarily be generating linear ramp waveforms with a max slew rate of about 0.3 V/us. This would be like 30 kHz tops. We would like to push the DAC update rate to 5 MHz or greater, but also require at least 18-bit precision. There is no analog front end in regards to sampling rate.
Strictly speaking the WR pulse only needs to be 20ns or 50MHz so updating at 5Mhz should be a problem. BUT....the distortion of this part will be poor because of the glitch energy. Each time the DAC updates there will be a glitch associated with the new code and the settling time, so the distortion on your 30kHz will be poor. The LTC2757 isn't really mean to be a signal generation DAC. The LTC1668 is better for signal generation, But if distortion and the glitch energy isn't a problem you might be ok.