A few questions about this DAC:
1) Based on the timing characteristics of the digital interface for Vdd = 3.3V, it should be feasible to update the LTC2757 at 16.66 MHz. However, if the output settling time specification in the datasheet is 2.1 us, does this mean that I should not being updating any faster than 476 kHz (or 555 kHz if optimizing settling time to 1.8us per Note 7)?
2) Is the settling time dependent on the step size? The datasheet states conditions for a span code = 000, which is 0-5V, but also states for a 10V step. In my experiments on the eval board, the size of the step didn't seem to affect the settling time.
3) I am having trouble understanding the graph of multiplying frequency response vs digital code. Why is there an individual line per bit rather than a single line for attenuation vs frequency?