My customer is considering AD5310R.
The AD5310R data sheet says “If SYNC is high after 16 falling clock edges occur, it is interpreted as a valid write and the first 16 bits are loaded to the input shift register.”
However, SPI Command Operation is all 24 bits.
Can the AD5310R "SHORT WRITE OPERATION" like the AD5681R?
Data Sheet AD5310R/AD5311R Rev. B
Data Sheet AD5683R/AD5682R/AD5681R/AD5683 Rev. D