I have a custom board with a pair of AD5791 DACs begin driven by a Xilinx Artix-7 FPGA. To test the performance of the DACs, I am using a DDS (Xilinx IP) within the FPGA to generate a 1 kHz tone. This DDS has a 20-bit output with Taylor series corrected noise shaping to allow for up to 114 dB SFDR.
When I look at the DAC output on a spectrum analyzer I see very large spurs at the harmonics of my tone, the largest of which are only ~50 dB below the tone itself. I would very much like to understand why I am unable to get closer to the 100 dB spec or even the 80-90 dB mentioned in this post. I am willing to provide more information as requested, including schematic snippets.
- My serial interface between the FPGA and DACs is synchronous to the DDS. SCLK is running at 25 MHz, and the SYNC_n update rate is 500 kHz.
- My measurements are not being performed synchronously (not providing a trigger to the spectrum analyzer).
- I have run a similar test on the AD5791 eval board using the digital interface header with similarly poor SFDR results.
What's the supply and reference voltage used?
Output buffer amplifier used?
And the spectrum analyzer model? What's the dynamic range of the equipment?
We are using a 14V supply, +/- 10V reference, and the same AD8675 output buffer amp as the eval board.
The spectrum analyzer is a Keysight N9030B. What would you like to know about the dynamic range that would be impacting the measurement of such large spurs? I am using the automatic attenuation setting in the spectrum analyzer to try to get the optimal mixer level. Feel free to reference the Keysight datasheet for the specific DANL and harmonic distortion numbers.
Can you try using these settings:
update rate: 65536 Hz
Clock speed: 8.33 MHz
I suggest making the update rate (DAC) and the sampling rate of the frequency analyzer synchronous.
Important to note that ADA4898-1 is recommended for low distortion AC applications.
What is the application for this circuit?
Unfortunately I have no easy way of synchronizing my frequency analyzer and my DAC with the board I am working on. It may be possible though and I will look into how I might do so when I have a chance.
As for the experiment you suggested, I was able to modify my DAC interface to use a 8.33 MHz SPI clock and a 65530.8 Hz update rate (100 MHz system clock divided by 1526). This yielded about a 3 dB improvement in my SFDR for a 1 kHz tone.
Is there some significance to using precisely a power-of-2 update rate?
The coherency of the signal plays a role when taking measurements in frequency domain.
Synchronizing will help, so does using an amplifier that is better suited for AC applications.