I have a custom board with a pair of AD5791 DACs begin driven by a Xilinx Artix-7 FPGA. To test the performance of the DACs, I am using a DDS (Xilinx IP) within the FPGA to generate a 1 kHz tone. This DDS has a 20-bit output with Taylor series corrected noise shaping to allow for up to 114 dB SFDR.
When I look at the DAC output on a spectrum analyzer I see very large spurs at the harmonics of my tone, the largest of which are only ~50 dB below the tone itself. I would very much like to understand why I am unable to get closer to the 100 dB spec or even the 80-90 dB mentioned in this post. I am willing to provide more information as requested, including schematic snippets.
- My serial interface between the FPGA and DACs is synchronous to the DDS. SCLK is running at 25 MHz, and the SYNC_n update rate is 500 kHz.
- My measurements are not being performed synchronously (not providing a trigger to the spectrum analyzer).
- I have run a similar test on the AD5791 eval board using the digital interface header with similarly poor SFDR results.