LTC2353-16, SPI Mode Unclear From Datasheet

Question

I've made a technical request on this, but wanted to put this here too. 
 When using the serial interface to communicate with the ADC, it seems as if the SPI write (SDI, to update softspan) requires a different mode than the output (SDO). The recommended output spi mode is not clear, with seeming contradictions within the document and with the actual behavior of the chip. 
 I using the LTC2353-16 in CMOS serial mode, communicating with an ATSAM4E16E. 
 The input uses idle-low SCKI, data valid on rising edge (SPI mode 0). However, the output SDO seems to update on SCKI rising edge and be valid on the falling edge (requiring an idle high, falling edge spi, mode 2). Here are the locations in the datasheet that contradict or are unclear. 
 p. 14 - Pin functions, under SCKI --Says input is valid (latches) on rising edge --Says output is valid (should be captured) on rising edge 
 
 p. 18 - Timing Diagram --Input is valid on rising edge --Output is not valid on rising edge. Output changes on rising edge and is valid on falling edge. 
 
 p. 18 timing diagram 
 p. 30-31 Serial CMOS Description --SCKI rising edges "clock conversion results" (which I take to mean updates the next output bit), which agrees with p. 18. --SCKI rising edges "latch" input softspan --Later in the section it says to capture output on rising edge of SCKI. This seems problematic because the output cannot both be updated and valid on the same edge. 
 My Results - My LTC2353-16 performs similarly to the timing diagram on p 18. I am pretty sure I get valid data when using the falling edge, and invalid data when using rising edge. 
 As far as I can understand the reality of the chip operation, it needs mode 0 to write softspan, and mode 2 to receive data from SPI, which I think is silly. 
 A response or clarification for the discrepancies in the datasheet would help. Thanks!

JeffreyGage · Accepted Answer

I got a reply from technical support in 2 emails going point by point. The engineer's response is bolded. Hope this helps if by some chance anyone else was wondering. 
 ----- 
 p. 14 - Pin functions, under SCKI --Says input is valid (latches) on rising edge - correct when using SCKI to sample data on SDI --Says output is valid (should be captured) on rising edge - correct when using SCKI to sample data on SDO0 and SDO1 (in text on page 31). It can also be captured using both edges of SCKO in DDR mode. p. 18 - Timing Diagram - this is just a general timing diagram without detailed timing information. see comments below. --Input is valid on rising edge --Output is not valid on rising edge. Output changes on rising edge and is valid on falling edge. p. 30-31 Serial CMOS Description --SCKI rising edges "clock conversion results" (which I take to mean each rising edge updates the next output bit), which agrees with p. 18. correct --SCKI rising edges "latch" input softspan correct --Later in the section it says to capture output on rising edge of SCKI. This does not agree with p 18, and seems problematic because the output cannot both be updated and valid on the same edge. In the center of figure 16 see the timing spec tHSDOSCKI which specifies a minimum 1.5ns that the current bit is valid. This assumes a 15pF load. This is what the data sheet says but the timing is very tight which makes me question why you wouldn't want to use the falling edge of SCKI to clock data into your FPGA. I'm checking with the factory engineer responsible for this part to confirm. My Results - My LTC2353-16 performs similarly to the timing diagram on p 18. As far as I can understand the reality of the chip operation, it needs mode 0 to write softspan, and Mode 2 to receive data from SPI, which I think is silly, so that's why I'm asking now. SCKI can be either high or low when the transfer is initiated. Data is clocked on the rising edge of SCKI so the SPI Mode can be either 0 or 3. See the attached application note. 
 [ Attached application note AN-1248 ] 
 A few additional timing comments from the LTC2353 factory application engineer: 
 It is possible to use the falling edge of SCKI if the SCKI frequency is less than 66.7MHz. Above that frequency the data is not guaranteed to be available at the falling edge. 
 Tskew is the time between SDO and SCKO. It is 0ns +/-1ns. SCKO is meant to be used with an FPGA where the skew can be adjusted inside the FPGA to guarantee it is captured properly.)

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LTC2353-16, SPI Mode Unclear From Datasheet