I've made a technical request on this, but wanted to put this here too.
When using the serial interface to communicate with the ADC, it seems as if the SPI write (SDI, to update softspan) requires a different mode than the output (SDO). The recommended output spi mode is not clear, with seeming contradictions within the document and with the actual behavior of the chip.
I using the LTC2353-16 in CMOS serial mode, communicating with an ATSAM4E16E.
The input uses idle-low SCKI, data valid on rising edge (SPI mode 0). However, the output SDO seems to update on SCKI rising edge and be valid on the falling edge (requiring an idle high, falling edge spi, mode 2). Here are the locations in the datasheet that contradict or are unclear.
p. 14 - Pin functions, under SCKI
--Says input is valid (latches) on rising edge
--Says output is valid (should be captured) on rising edge
p. 18 - Timing Diagram
--Input is valid on rising edge
--Output is not valid on rising edge. Output changes on rising edge and is valid on falling edge.
p. 18 timing diagram
p. 30-31 Serial CMOS Description
--SCKI rising edges "clock conversion results" (which I take to mean updates the next output bit), which agrees with p. 18.
--SCKI rising edges "latch" input softspan
--Later in the section it says to capture output on rising edge of SCKI. This seems problematic because the output cannot both be updated and valid on the same edge.
My Results - My LTC2353-16 performs similarly to the timing diagram on p 18. I am pretty sure I get valid data when using the falling edge, and invalid data when using rising edge.
As far as I can understand the reality of the chip operation, it needs mode 0 to write softspan, and mode 2 to receive data from SPI, which I think is silly.
A response or clarification for the discrepancies in the datasheet would help. Thanks!