The Following is a brief description of the AD5686R Spice Macromodel
The Spice Netlist can be downloaded from the AD5686R product page:
The AD5686R spice MacroModel does not model the Serial Interface as per the datasheet, instead it contains a simple parallel interface. The simple parallel interface contains the following signals:
The parallel interface makes it much easier to load data into the DAC, for example, to run a simulation where the DAC output moves from zero-scale to full-scale a single PWL source can be used to drive the 16 parallel inputs and another PWL source can be used to drive the STROBE and DACLoad signals. The STROBE and DACLoad signals can be tied together or driven separately.
The AD5686R Spice MacroModel contains 4 pins that can be used to select a channel, these are called CH_A, CH_B, CH_C and CH_D. When any of these pins are high the corresponding channel output will be updated on the rising edge of DACLoad. When these pins are held low the corresponding channel output will not be updated on the rising edge of DACLoad. This feature allows each channel to be updated simultaneously or at different times.
What specifications and features are modeled:
Slew Rate, Settling time, capacitive load stability, offset error, Zero Code Error, Gain Error, DC Crosstalk, DC PSRR. RESET pin functionality, RSTSEL pin functionality, GAIN pin functionality, short circuit current, IDD, ILOGIC
Typical values, as per the datasheet, are used for most of the above specifications. It is possible for the user to change the value of the zero code error, gain error and offset error using the .param statement in the simulator. For example, pressing F11 in SIMetrix opens the command window where the .param statement can be entered. The values entered should be in volts. The gain error is specified as %FSR in the datasheet but this must be converted to volts for use in the .param statement (0.02%FSR = 499.99µV). The following example overwrites the typical vales with the maximum values:
The PwrOn parameter sets the value that the DAC outputs power up to, 0 = zero-scale and 1 = mid-scale:
What is not modeled:
Temperature coefficients, Serial Interface functionality and timing, SCLK pin, SYNC pin, SDIN pin, SDO pin, LDAC pin, daisy chain and readback modes, Software functions, noise, Turn On/Turn Off time, leakage currents, output stage power down circuitry, etc.