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AD5292 AD5293 Internal Shift Register Content After SYNC Went High


With the AD5292 and AD5293 a high edge on _SYNC either has the chip consider the bits in the shift register as command or data, or it has the chip consider that edge as a PSI reset, if the number of clock edges was no multiple of 16.

What happens with the values in the shift register after that or at/before the _SYNC goes low again?

If I daisy chain ten AD5292 and want to only talk to the first five, can I then just clock in the 80 bits for the first 5 devices and raise _SYNC in order to let the 5 chips output their data, and do this several times?

Like after _SYNC goes high (and the data is considered or not, depending on the clock cont being a multiple of 16), are the shift register bits reset, or do the values keep stored and are used by the last five chips, if I only clock 80 new data bits in the next time again?



Typo in title
[edited by: GerdF at 1:21 PM (GMT 0) on 23 Apr 2020]
  • Ok, the device counts only negative SCLK edges.

    But even if the device does not remember the number of clock pulses of the previous transmission, there is still the content of the shift register.

    For the actual device this does not matter at all. But if one wants to reuse the shift register content, as you suggested in April, it would matter if having a positive edge before SYNC goes high would do some additional shifting.

    It seems like the shift register is a double action design, that shifts from DIN to an internal register on the negative edge of SCLK and then shifts it like a half bit further. Maybe the second action is just some kind of preparation for the next shift with a negative edge. In that case, the additional positive edge should not matter, as there is only two times preparing but still only one time shifting (with the negative edge).

    I assume you have not found a GPIO expander from Analog Devices? Matching the daisy chain with the Maxim part is quite a PITA as you might be able to tell from my many heavily detailed questions here...

  • We do not have a GPIO expander.

    If there are 32 SCLKs or its multiples in case of Daisy Chain, then the device shift register will get updated. Now, if you are providing 33 or 31 SCLKs or its multples, the write operation will not succeed. Now, it is for your system to understand and ignore the data if you want to provide SCLKs other than the count of 32 or its multiples. For the read operation, the internal shift register does not get erased, unless the device is performing a transaction to update it. So, your assumptions above are invalid. 

    Have you observed such behavior on your system that you have stated above. ?