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AD5292 AD5293 Internal Shift Register Content After SYNC Went High

Hi,

With the AD5292 and AD5293 a high edge on _SYNC either has the chip consider the bits in the shift register as command or data, or it has the chip consider that edge as a PSI reset, if the number of clock edges was no multiple of 16.

What happens with the values in the shift register after that or at/before the _SYNC goes low again?

If I daisy chain ten AD5292 and want to only talk to the first five, can I then just clock in the 80 bits for the first 5 devices and raise _SYNC in order to let the 5 chips output their data, and do this several times?

Like after _SYNC goes high (and the data is considered or not, depending on the clock cont being a multiple of 16), are the shift register bits reset, or do the values keep stored and are used by the last five chips, if I only clock 80 new data bits in the next time again?

Regards,

Gerd



Typo in title
[edited by: GerdF at 1:21 PM (GMT 0) on 23 Apr 2020]
  • Hi,

    Someone is currently looking into your query and will respond as soon as possible.

    Cheers,

    Ivan

  • If the clock edges are not multiple of 16, then the write or read sequence relevant to the partial sequence will be ignored, as soon as the /SYNC goes high. Only the valid read or write sequences having 16 bits or its multiples will be accepted.

    Yes, in daisy chain, you can talk to the first five by clocking in 80 bits.

    Data coming out on SDO lines will act as the command sequence to the SDI of the next part. Serial register data do not get reset on /SYNC going high. Your purpose to retain previous serial register data to act as command to next device will not work in all cases.

    What will come out on SDO line in the next frame is decided by the command sequence provided in the current frame for the same part.

    If you look at Table 11 in the AD5293 DS, then the read commands will change the SDO data contents in the next frame.

    There is an example Table 09 to explain the same clearly.

  • "Serial register data do not get reset on /SYNC going high."

    Ok, that's what I needed to know. Many thanks!

    Although, my purpose was not to reuse the data for the first 5 ICs on the second five ICs, but I had hoped that the serial shift register would be reset to all zeros, so that I could have always just delivered 80 fresh bits in order to write to the first five ICs, and only cared about the second five ICs if I would have wanted to write to them.

    As the shift register is not reset on /SYNC going high, I will have to provide 80 zeros first (NOP for the second five ICs), followed by  80 relevant data bits (for the first 5 ICs) and then deassert /SYNC.

    Or I use a GPIO pin to either mask the /SYNC signal for the second five ICs or to switch on and off the pull-up line for the SDO pull-up resistors connected to ICs 4-9.

  • Yes, you will have to provide 5 NOPs for the second set of 5 ICs followed by 5 commands for the first set of 5 ICs if configured in daisy chain.

  • With all the commands, DB15 and DB14 are meant to be 0. What happens if one or both of them are 1 ?

    Does the command associated with DB0 to DB13 get executed anyway (then there shouldn't be 0s but rather Xs), is the sequence ignored (just like with the NOP command) or is the behavior unspecified and therefore dangerous?

    I would like to put another IC on the same daisy chain as the AD5292s and might have to write to this other IC quite often. If the AD5292 would ignore any command not having two 0s as DB15 and DB14, I could just dispense with first clocking like 160 zeros into the chain but only use the 16 bits for the other IC, at least if that 16 bit word has DB15 or DB16 set to 1.

    Still another question regarding the AD5292 SPI interface:

    Figure 53 shows the digital feedthrough. Is this with a full active command transferred (presumably during the short peak up to 32µV) followed by the command taking place (taking about 5 to 7µs), or would such a peak be the result of a simple input line (like SCLK or DIN) toggle?

    If the former would be the case, do you have data on digital feedthrough with an NOP command or with the toggling of /SYNC, SCLK or DIN?

    Like if the analog circuitry would be adequately shielded from SCLK or DIN transitions at least if /SYNC of that particular IC is held high.

    And last but not least: Does ADI have an affordable GPIO IC that is compatible with the SPI daisy chain system used by the AD5292? I seem to be a little blind at the moment.
    I found something I could use in the MAX7317, but firstly it has the opposite CLK polarity and secondly it would be the only non-ADI IC on the board and why not go full-ADI if it would be possible...

  • With all the commands, DB15 and DB14 are meant to be 0. What happens if one or both of them are 1 ?

    Does the command associated with DB0 to DB13 get executed anyway (then there shouldn't be 0s but rather Xs), is the sequence ignored (just like with the NOP command) or is the behavior unspecified and therefore dangerous?

    >>>>  Yes, DB[15:14] are meant to be 0 for proper operation. All other bit values are intended for internal use and not recommended for the user.

    I would like to put another IC on the same daisy chain as the AD5292s and might have to write to this other IC quite often. If the AD5292 would ignore any command not having two 0s as DB15 and DB14, I could just dispense with first clocking like 160 zeros into the chain but only use the 16 bits for the other IC, at least if that 16 bit word has DB15 or DB16 set to 1.

    >>>>>> You need to ensure that the AD5292 get the right command in the daisy chain mode with DB[15:14] set to 0..

    Still another question regarding the AD5292 SPI interface:

    Figure 53 shows the digital feedthrough. Is this with a full active command transferred (presumably during the short peak up to 32µV) followed by the command taking place (taking about 5 to 7µs), or would such a peak be the result of a simple input line (like SCLK or DIN) toggle?

    If the former would be the case, do you have data on digital feedthrough with an NOP command or with the toggling of /SYNC, SCLK or DIN?

    Like if the analog circuitry would be adequately shielded from SCLK or DIN transitions at least if /SYNC of that particular IC is held high.

    >>>>> Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. SYNC is held high while the SCLK and DIN signals are toggled.

    And last but not least: Does ADI have an affordable GPIO IC that is compatible with the SPI daisy chain system used by the AD5292? I seem to be a little blind at the moment.
    I found something I could use in the MAX7317, but firstly it has the opposite CLK polarity and secondly it would be the only non-ADI IC on the board and why not go full-ADI if it would be possible...

    >>>> Thanks for your interests in ADI products. I will enquire internally and get back to you.

  • Hi,

    in the timing diagrams in the datasheets for the AD5292/5291 and AD5293, /SYNC is always brought high before SCLK is brought high.

    Would it be OK, if SCLK would be brought high before /SYNC at the end of the transmission?

    I would think that it should be no problem because no new DIN sampling would be triggered by the low-to-high transition of the SCLK. Also the specified setup and hold times related to SCLK and /SYNC (t4, t7 and t9) are only about falling edges of SCLK and not about rising edges.

    What might matter though, could be the fact that with the rising edge of SCLK the next value in the row is driven on the SDO line.

    While I assume that this does not mess with the function of the actual command that is decoded on the rising edge of /SYNC, there might be some confusion if the rising edge of SCLK triggered the driving of the next value to the SDO line, as the next Transaction will begin with a rising SCLK edge. Would that cause an additional shift in the shift register or would it be ignored because there would firstly have to be a negative edge of SCLK (while /SYNC is low)?

    Regards,

    Gerd

  • SCLK can be brought high before SYNC at the end of the transmission. It is the falling edge of SCLK that matters with SYNC as defined by parameter t9. However, it will result in an additional shift in the shift register and the SDO update with the rising edge of the SCLK. 

  • Ok, that's what I assumed.

    Thank you very much for the confirmation.

    This additional shift and the SDO update would not hurt per se, but I wonder what then would happen with the next transmission, because there would be also a positive (rising) SCLK edge before the negative edge with which the new DIN value would be sampled.

    Would this rising edge be kind of ignored because the shift and SDO update had already been done by bringing SCLK up before SYNC at the end of the previous transmission? Or would it result in an extra shift or other disturbances?

  • In each frame 32 falling edge of SCLKs are needed for write operation. So, as long as the SYNC remains low with exact 32 SCLKs, the write operation will happen. If the SYNC goes high atleast one SCLK earlier or later, the write operation will be ignored provided it is for a single device.. The device does not remember the number of SCLKs in a previous frame.It just count the number of SCLKs in the current frame and take updates if the number of SCLKs are correct.