AD5696 Vref power up behaviour

Recently i got a power up issue of a external reference circuit for AD5696, it resulted in a lower then expected reference voltage.

The reason for this was the Vref-Input of AD5696. It actually started to output 2.4V a few ms earlier then the reference. This doesn't occurs always but more in a random way.

Once the AD5696 starts outputing on Vref, it loads the reference voltage with several mA and keept it on the lower level.

As soon as the nRESET-Pin of AD5696 goes high, Vref-Pin switchs back to input state and everything is fine again.

Additional nRESET cycles don't change this input state back to output. Thus all good from this point on.

Just want to share this information, as it might have other side effects in other designs.

So far it is no real issue in my design anymore.

    •  Analog Employees 
    on May 15, 2019 2:04 AM over 1 year ago

    Hi ,

    Are you indeed using the AD5696 and not the AD5696R? 

    Have you tried setting /RESET pin as logic high before supplying and enabling the external reference and see what happens?

     

    Cheers,

    Ivan

  • Yes that fixed the issue. Once /RESET is high before Vdd is powered, everythin worked like a charm. That requires powering Vlogic earlier then Vdd as well, due to internal protection diodes.

    An additional interesting point here is, if NRESET is left low during power up, then a undefined DAC-output is generated.

    Well at least i hope it is a AD5696. It is marked with

    AD5696

    ARUZ

    #743

    And once it correctly leaves Reset state it always accepts the external reference.

    The same powering thing is true for RSTSEL pin.

    And the reset behaviour in conjunction with RESET and RSTSEL seems to be interesting as well:

    RSTSEL state

    Vlogic state

    /RESET state

    Result

    Low

    Power up to late (my bad design)

    High

    Start with DAC output = 0V

    High

    Power up to late (my bad design)

    High

    impossible state due to DAC internal protection diodes

    High

    Vlogic powered before Vdd

    High

    Start with Midscale, but later /RESET low results in 0V output again (? good to know)

    Low

    Vlogic powered before Vdd

    High

    Start with DAC output = 0V

    Low

    Power up to late (my bad design)

    Low

    Start with DAC output = 0V

    Low

    Vlogic powered before Vdd

    Low

    Start with DAC output = 0V

    High

    Vlogic powered before Vdd

    Low

    Start with random DAC-output until /RESET goes High

    Hope that is now the complete startup behaviour of AD5696.