The AD5770R is a 6-channel, 14-bit resolution, low noise, programmable current source digital-to-analog converter (DAC). The AD5770R contains five 14-bit resolution current sourcing DAC channels and one 14-bit resolution current sourcing/ sinking DAC channel.

Q1. What Output current ranges are available on the AD5770R, are they software selectable?

The following ranges are available and selectable by software:

  • Channel0: 0mA to 300mA, -60mA to 300mA, -60mA to 0mA
  • Channel1: 0mA to 140mA (Low Headroom), 0mA to 140mA (Low Noise and PSRR), 0mA to 250mA
  • Channel2: 0mA to 55mA, 0mA to 150mA
  • Channel3, Channel4, Channel5: 0mA to 45mA, 0mA to 100mA

Q2: Can the AD5770R be configured as a precision current sink:

Yes!, Channel0 [IDAC0] has two current sink ranges: -60mA to 0mA and a -60mA to +300mA range. 16 bit resolution is guaranteed on all current source and current sink ranges.

Q3: How can the AD5770R achieve an output current of 0mA?

To set 0mA for any combination of channels the output stage should be disabled (placed in High-Z) by asserting the corresponding CHx_SHUTDOWN_B bit in the CHANNEL_CONFIG register (address 0X14).

Q4: Can the output current be increased by summing channels ?

Yes!, individual channels can be directly connected together to increase the output current range. However, the voltage at the IDAC pins must stay within the compliance voltage range. For example, IDAC1 can be connected to IDAC2 to obtain a full scale output current of +400mA. At +400mA the voltage at the IDAC[2:1] pins must exceed PVDD[2:1] – 0.45V

Q5: Can the full scale output current ranges be decreased?

Yes!, The AD5770R has a range scaling feature whereby all the current sourcing ranges can be scaled back from 1.0X to 0.5X while maintaining 14 bit monotonicity. The full-scale output current of any channel can be scaled by writing to the CHx_OUTPUT_SCALING bits of the OUTPUT_RANGE_CHx register.

IADJ is the adjusted full-scale output current.
INOM is the nominal full-scale output current.
x is the code loaded into output scaling register, 0 ≤ x ≤ 63.

Q6: How does the compliance voltage, specified in table 1 of the AD5770R Datasheet, scale with output current?

The output compliance voltage will increase as the output current decreases. In other words, the headroom voltage, also known as dropout voltage, of each IDACx output will decrease as the output current decreases. For example, Channel0 in Figure 41 below, the dropout voltage (headroom) is typically 350mV at 300mA, but at 200mA the dropout voltage is typically 225mV.   

Q7: What exactly is the output compliance voltage?

When sourcing current, the output compliance voltage is the maximum voltage at the IDACx pin, for which the output current is within 0.1% of the measured full-scale range. When sinking current on Channel 0, the output compliance voltage is the minimum voltage at the IDAC0 pin, for which the output current is within 0.1% of the measured zero-scale current.

Q8: Why is there a dedicated PVDDx pin for each IDAC output and can they all be tied to a single supply voltage?

Having dedicated PVDDx pins allows the AD5770R to become very power efficient. For example, if Channel0 had a load voltage of 2.5V when sourcing 300mA then PVDD0 would need to be at least 2.95V. If the remainder of the channels, Channel[5:1], only had a load voltage of 1.5V each, they only require a voltage of 1.8V on PVDD[5:1]. Since each channel has a dedicated PVDDx supply pin, PVDD0 can be powered from 2.95V and PVDD[5:1] can be powered from 1.8V, resulting in a reduction of the on chip power dissipation.

All PVDDx pins can be connected to the same supply, however the voltage must be chosen to ensure all IDACx outputs remain within the compliance voltage range. This will be set by the channel with the highest voltage on its IDACx pin.

Q9: What is the minimum value of PVDDx.

The minimum value if PVDDx is 0.8V. It is recommended that PVDDx is kept as low as possible for each channel to reduce power dissipation in the part.

Q10: What function does the monitor mux perform?

The monitor mux allows the following parameters to be measured:

  1. Output Compliance Voltage: When monitoring Output Compliance Voltage the actual output voltage for the selected channel is available on the MUX_OUT pin
  2. Output Current: When monitoring output current, a voltage representation of the selected channel output current is made available on the MUX_OUT pin. The output current can be calculated using:

  1. Die Temperature: When monitoring die temperature, a voltage representation of the on chip die temperature is made available on the MUX_OUT pin. The die temperature can be calculated using:

Q11: Can the AD5770R automatically shutdown to protect itself if the junction temperature becomes too high?

Yes!, the AD5770R has an overtemperature warning and an overtemperature shutdown. The overtemperature warning occurs at 125DegC and is flagged by the ALARM pin and the corresponding bit in the status register. The overtemperature shutdown occurs at 150DegC, on occurrence all six IDACx outputs will be automatically shutdown, the ALARM pin and corresponding bit in the status register will be asserted.

Q12: Is it possible to load all DAC or INPUT registers by the same code in a single SPI write?

Yes!, the DAC_PAGE_MASK and INPUT_PAGE_MASK registers allow any combination of DAC and Input registers to be loaded with the same code in a single SPI transaction.

Q13: Is there a Software and Hardware LDAC function on the AD5770R?

Yes!, the AD5770R has a hardware LDAC pin (pin F6) and a software LDAC function (SW_LDAC register, address 0x37). The Hardware LDAC pin can be ignored (masked) for any combination of channels by writing to the HW_LDAC register at address 0x25. A Software LDAC can be issued for any combination of channels by writing to the SW_LDAC register at address 0x37.

Q14: What function does the background CRC feature provide?

The AD5770R periodically performs a background cyclic redundancy check (CRC) on the status of the on-chip registers to make sure memory bits are not corrupted. In the unlikely event that the background CRC fails, the ALARM pin will be asserted low and the corresponding bit in the STATUS register will be set.

[edited by: clon at 8:38 AM (GMT 0) on 16 Feb 2019]