AD4131-8 SPI communication

Issues with AD4131-8 SPI communication and timing see below in resolving AD4131-8 SPI communication and timing issues. The Power-On Reset stage involves a Treset_delay during which CS and SCLK remain inactive, and that the software reset is distinct from the automatic power-up reset. The SPI interface behavior for AD4131-8 is that the DOUT/nRDY remains in tristate when nCS is high regardless of 3- or 4-wire mode, and the device only responds to SCLK when nCS is low, consistent with SPI standards. It's advised to implement hardware compliant with SPI requirements for proper connection and control of AD4131-8 with other SPI devices. Advisable to check the datasheet's digital section and signal behavior.