Yes, setting the SING_CYC bit will allow this. It should be noted that the Sinc5+Sinc1 filter will settle in a single cycle at output data rates of 10 kSPS and lower regardless of whether the SING_CYC bit is set or not.
AD7175-2
Recommended for New Designs
The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-
channel (fully/pseudo differential) Σ-Δ analog-to-digital converter
(ADC) for low bandwidth...
Datasheet
AD7175-2 on Analog.com
Yes, setting the SING_CYC bit will allow this. It should be noted that the Sinc5+Sinc1 filter will settle in a single cycle at output data rates of 10 kSPS and lower regardless of whether the SING_CYC bit is set or not.