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The AD7768 is an 8-channel, simultaneous sampling Σ-Δ analog-to-digital converter (ADC) with a Σ-Δ modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals. The AD7768 achieves 108 dB dynamic range at a maximum input bandwidth of 110.8 kHz, combined with typical performance of ±2 ppm integral nonlinearity (INL), ±50 μV offset error, and ±30 ppm gain error.

Two important commands on the AD7768 are the SYNC and RESET commands. This FAQ aims to clarify the difference between the two functions, what they do, and when they are required.


The SYNC command can be thought of as a reset of the digital filter paths and logic within the AD7768. One of the major events that the sync triggers is the reloading of the digital filter coefficients based on the selected configuration. A SYNC should be provided to the AD7768 after any changes to the AD7768 configuration, before valid samples are acquired. It should also be provided after a RESET or after initial power-up when in pin control mode or when no SPI configuration changes are required.

If a SYNC is not provided after a configuration change, then, for example, the digital filter coefficients used may not be correct for that configuration. In this case, an unexpected filter profile could be used, until a SYNC is provided.

The sync signal can be provided direct to the AD7768 SYNC_IN pin, to the START pin, or can be triggered over SPI, under software control. To provide the SYNC over SPI or through the START pin, the SYNC_OUT and SYNC_IN pins must be tied together.

Once the SYNC is provided, it is no longer required to provide a SYNC again, until either the part is reset, or the configuration is changed.


The RESET command causes a full reset of the AD7768, and the device is set to it's default configuration. It is useful to put the AD7768 into a known valid configuration, with all internal registers set to default values.

The default configuration is as follows:

- Eco power mode with MCLK/32.

- Interface configuration of DCLK = MCLK/8, header output enabled, and CRC disabled.

- Filter configuration of Channel Mode A and Channel Mode B is set to sinc5 and decimation = ×1024.

- All channels are assigned to Channel Mode A.

- Analog input precharge buffers are enabled on all channels.

- Reference precharge buffers are disabled.

- The offset, gain, and phase calibration registers are reset to the factory settings.

- Continuous conversion mode is enabled.

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