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data sheet error. Hold time of A0 and A1 signal during SPI transfert on AD2S1210

Q 

T33, The hold time for A0, A1 do not seem to be correct or aligned to the
parameters.

 

A 

It should be related to SPI clock and not the CLKIN frequency.

A0 and A1 should hold their value for the duration of the data read and after
that they can be released or set to a new state.

Upon review and analysis wrt AD2S1210 datasheet.  There appears to have typo
errors in the timing parameters. Have liaison with the author for this
datasheet.

The hold time for A0, A1 should be related to SPI
clock and not the CLKIN frequency. Currently the datasheet is being revise to
include these changes. Please see attached temporary cut down version for the
time
being.

Comments
Anonymous
  • in reply to jcolao

    Thank you jcolao, one last question, Do you know what is the SPI operational mode on the R/D converter?

    is it Mode 3 ( CPHA=1 and CPOL=1) ? I appreciate your time.

    Thanks,

    Ish

  • in reply to ismagine

    Hi Ish,

         The AD2s1210 CLKIN and SCLK can work independently. SCLK frequency is dependent on the Vdrive supply with 20Mhz at Vdrive from 4.5V to 5.25V. The AD2S1210 is an SPI compatible interface. To use it as a serial interface, the /SOE pin must be held low and can start input a frequency on the  SCLK pin and with pin DB14 as the SDI and pin DB15 as SDO.

         For the T33, I will get back to you on that changes as mentioned on the previous post.

    Regards,

    Jonathan

  • I have a similar problem. What is the maximum SPI clk frequency for a 8.192 MHz Crystal? According to the diagram t33 would be around 33us, is this valid? Can I have higher SPI clock than  CLKIN?

    One last question, what is the SPI Mode for the AD2S1210? is it SPI mode:3? (This mode is used on the AD2S100x models where SDO signal is shifted out on the rising edge SCLK and available on falling edge, but the information on the AD2S1210 is vague)

    Regards,

    Ish

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