Question We are planning to use the AD7091R in a mobile low power distance measurement device. We need a data throughput of 1MSMP/S. My question is if it is possible to readout the data by SPI during a conversion. At the datasheets there are only examples in which the data a readout by SPI after a conversion. This means that I need a very high SPI clock when I want to use the ADC at 1MSPS. Answer After testing an eval board, the answer to the question is yes. In fact this is how it's done on the SDZ eval board as the SDP is limited with maximum clock speed. The caveat here is that tQUIET of 50ns min is violated when doing this. The part was never evaluated/tested for this condition, and we can't guarantee specified performance when running the part in this manner. It is also essential that any reading of data from the SDO line is completed before EOC. The output register is updated with the next result at EOC.

Is it possible to get a PCB footprint for the AD7091?

Question Is it possible to get a PCB footprint for the AD7091? Answer Yes a .bxl file for the AD7091 can be downloaded from http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7091/produ cts/symbols-footprints.html This file can be opened in the Ultra Librarian Reader also available for download at the same location. This tool can then export the bxl file to the PCB design tool required.

If a second /CONVST pulse occurs before the end of conversion point, EOC, what will happen? Will the first request be cancelled and a new conversion begun?

Question If a second /CONVST pulse occurs before the end of conversion point, EOC, what will happen? Will the first request be cancelled and a new conversion begun? Answer Once a conversion is started by pulling the /CONVST pin low if the /CONVST pin is brought low again before the EOC point the second request is ignored and the result of the first request will be available as normal once the original conversion time has elapsed.

Do I need an external pull up resistor on the SDO pin if the Busy Indicator feature is not required?

Question Do I need an external pull up resistor on the SDO pin if the Busy Indicator feature is not required? Answer No. An external pull up resistor is only required if the Busy Indicator feature is used. When the Busy Indicator feature is used the SDO pin goes from three-state to active low at the EOC point. To ensure this change can be detected by the input to a controller the pull up resistor ensures the three-state condition is seen as a high level at the controller.

Are there IBIS models available for the AD7091 LFCSP package?

Question Are there IBIS models available for the AD7091 LFCSP package? Answer There is currently no IBIS model available for the AD7091. There is a AD7091R IBIS model for the MSOP package that can be downloaded at the following link: http://www.analog.com/en/analog-to-digital-converters/ad-converters/AD7091R/prod ucts/tools-software-simulation-models/index.html The characteristics for the AD7091R MSOP package and the AD7091 LFCSP package should be similar so it is recommended to use this model in simulations for the AD7091.

Can the ADC input exceed the supply voltage or go below ground?

Question Can the ADC input exceed the supply voltage or go below ground? Answer The ADC input should not exceed the supply voltage or go below ground by more than 0.3V as this may result in the ADC being damaged. If this is a common condition then schottky diodes should be used to protect the input and limit it

AD7091: Can Vdrive be greater than Vdd

Question Can Vdrive be greater than Vdd? Answer Yes, Vdrive can be greater than Vdd. It should be noted that if the 1LSB INL specification is important to the application then Vdrive should not exceed Vdd by more than 0.7V. Also the performance limit for Vdd and Vdrive is 5.25V.

AD7091R IDRIVE current higher than 20uA

Question Why when I measure the Idrive current during operational mode do I get higher than the 20uA as quoted in the maximum rating in the data sheet? Answer The conditions for Idrive current measurements in the data sheet are for a Vin = 0V. This means that the output codes are all 0s. If the output codes are toggling the current required to change the state of the SDO pin is increased and the Idrive current is increased. The worst case current will be when the conversion result is 101010… Cftl CN0247 can be viewed at the following location: http://www.analog.com/en/circuits-from-the-lab/CN0247/vc.html This gives the current draw on Idrive when a 10kHz input signal is applied and a 1 MSPS sampling rate. The typical Idrive current is 409uA in this example. The current drawn in a particular application will also depend on the capacitive load on the SDO line.

AD7091R: Second /CONVST pulse occurs before the end of conversion point

Question If a second /CONVST pulse occurs before the end of conversion point, EOC, what will happen. Will the first request be cancelled and a new conversion begun? Answer Once a conversion is started by pulling the /CONVST pin low if the /CONVST pin is brought low again before the EOC point the second request is ignored and the result of the first request will be available as normal once the original conversion time has elapsed.

AD7091R IBIS Model LFSCP and MSOP

Question Are there IBIS models available for the AD7091R LFCSP and MSOP package? Answer There is an IBIS model available for the AD7091R MSOP package that can be downloaded at the following link: http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7091r/prod ucts/tools-software-simulation-models/index.html The characteristics for the MSOP package and the LFCSP package should be similar so it is recommended to use this model in simulations for the LFCSP package.

AD7091R MSB always 0 after each conversion

Question Why after every conversion is the MSB of the conversion result always “0”? Answer If the communication timing is ok this is usually due to the time between the /CONVST start pulse going low and reading back the conversion. The conversion time is 650ns maximum. If the result is read back before this time has elapsed then it is possible that the MSB will be zero. You can also use the BUSY indication feature to indicate when a conversion is complete by having /CS low prior to the EOC point. This will take the SDO line out of high impedance once a conversion completes and this can be detected by the SPI master.

AD7091R Conversion Result Change - Documents - Precision ADCs

AD7091R Conversion Result Change

Question

After powering up the device why does the conversion result change after
approximately 60 samples have completed?

Answer

After power-up ensure that the software reset as outlined in the data sheet is
completed.
A software reset initializes the AD7091R and ensures correct conversion
results. The device will eventually initialize correctly after a certain number
of conversions without a software reset but it is recommended for correct
operation to always perform a software reset after a power cycle.

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AD7091R Conversion Result Change