Q
I need an help to configure an AD7190 to sample channel (+)AIN1 (-)AINCOM.
I try to set the the configuration register to work with this channel, but when
i read the conversion, the status register report a wrong value (0x05).
This is the initialization I sent to the ADC:
ADC_reset();
sleep(100);
// GPOCON register
adc_write (0x28); // 0b0010.1000
adc_write (0x00); // 0b0000.0000
// CONFIGURATION register
adc_write(0x10); // 0b0001.0000
adc_write(0x00);
adc_write(0x10); // <= AIN1
adc_write(0x18);
// MODE register (24 bit)
adc_write(0x08); // 0b0000.1000
adc_write(0x18); // 0b0000.1000
adc_write(0x04); // 0b0000.1000
adc_write(0x10); // 0b0000.1000
Just for testing I report different configuration and response I've got from
the ADC:
CONF => STATUS
0x01 => 0x01
0x02 => 0x01
0x04 => 0x03
0x08 => 0x03
0x10 => 0x05
0x20 => 0x05
0x40 => 0x07
0x80 => 0x07
I can't understand where is my mistake.
For the later:
In my application I need to use AIN1->AINCOM and AIN2->AINCOM with the channel
sequencer.
I suppose I should send 0x30 as channel selection, right?
A
Your code is correct. Looking at the bits returned from the status register,
the LSB is always set to 1. When the ADC has output the conversion and the
contents of the status register, the DOUT/RDY pin stops functioning as a DOUT
pin and begins functioning as a DRDY pin. This happens some period of time
after the last SCLK rising edge. This same SCLK edge to used to latch the LSB
of the status register. If the processor is slow, it is possible that the
DOUT/RDY pin has started functioning as a DRDY pin so the processor latches the
value of DRDY which is '1' rather than latching the LSB of the status register.
With this slow processor, the LSB of any read (from an on-chip register or a
conversion) will be zero.
So, you need to use a faster processor. Another option is to bit bang i.e. use
general purpose input/output pins to replicate the serial interface. Using this
method, you can read the bits a period of time after the SCLK falling edge
rather than using the SCLK rising edge. So, the correct bits are always read.
Regarding you last query, you are correct - to enable channels AIN1-AICMOM and
AIN2-AINCOM, set the channel bits to 03 hex.
