Analog.com Analog Dialogue Wiki English 简体中文 日本語
EngineerZone
EngineerZone
  • Log In
  • Site
  • Search
  • User
  • Forums

    Popular Forums

    • RF and Microwave
    • Power Management
    • Video
    • FPGA Reference Designs
    • Precision ADCs
    • Linux Software Drivers
    • SigmaDSP Processors & SigmaStudio Dev. Tool

    Product Forums

    • A2B
    • Amplifiers
    • Analog Microcontrollers
    • Clock and Timing
    • Data Converters
    • Direct Digital Synthesis (DDS)
    • Energy Monitoring and Metering
    • Interface and Isolation
    • MEMS Inertial Sensors
    • Processors and DSP
    • Switches/Multiplexers
    • Temperature Sensors
    • Voltage References
    View All

    Application Forums

    • Audio
    • Automated Test Equipment (ATE)
    • Condition-Based Monitoring
    • Depth, Perception & Ranging Technologies
    • Embedded Vision Sensing Library
    • Motor Control Hardware Platforms
    • Optical Sensing
    • Precision Technology Signal Chains Library
    • Video
    • Wireless Sensor Networks Reference Library

    Design Center Forums

    • ACE Evaluation Software
    • ADEF System Platforms
    • Design Tools and Calculators
    • FPGA Reference Designs
    • Linux Software Drivers
    • Microcontroller no-OS Drivers
    • Reference Designs
    • Signal Chain Power (SCP)
    • Software Interface Tools
    • System Demonstration Platform (SDP) Support
  • Learn

    Highlighted Webinar

    Maximize the Benefits of High Bandwidth Current Sense Amplifiers for Space Constrained Applications

    Recent Discussions

    • Pluto is not receiving data
    • ADALM-pluto sampling frequency
    • ADALM PLUTO SDR
    • Bad FIT image format and MSD mounting errors in firmware built for Sidekiq Z2
    • set the sample rate to 30MHz or the maximum that usb2.0 allows

    Places

    • ADI Education Home
    • ADI Webinars
    • StudentZone (Analog Dialogue)
    • Video Annex
    • Virtual Classroom

    Latest Webinars

    • Maximize the Benefits of High Bandwidth Current Sense Amplifiers for Space Constrained Applications
    • Design Efficient Power Solutions for Battery-powered Applications
    • Shunt-based Energy Metering in High-Power Applications
    • Isolating GigaSpeed: Unlocking Data Integrity for USB and HDMI Communication
    • Extend Battery Life and Maximize Performance - Let Supervisors Do The Work
    View All Webinars
  • Community Hub

    Challenge Yourself!

      KCC's Quizzes AQQ244 about Wafer Processing Yield puzzle
    View All

    Places

    • Community Help
    • Logic Lounge
    • The Weekly Brew

    Resources

    • EZ Code of Conduct
    • Getting Started Guide
    • ADI: Words Matter
    • Community Help Videos
    View All
  • Blogs

    Highlighted Blogs

    The Changing Nature of Logistics and Retail Automation

     

    Variable Speed Drive 101

    Latest Blogs

    • How to Optimize Voltage Regulators for Powering an Audio Amplifier
    • EMC Standards: What Are They, and Why Do They Matter?
    • Understanding Grating Lobes with the Phaser (CN0566) Exploration Kit
    • Digitizing, Connecting, and Delivering Energy Efficiency – the Future of Intelligent Buildings
    • Pain or Injury
    Read All Blogs

    ADI Blogs

    • EZ Spotlight
    • The Engineering Mind
  • Partners

    Electronic Design Services - PartnerZone

    • Boston Engineering
    • Calian, Advanced Technologies
    • Colorado Engineering Inc. (DBA CAES AT&E)
    • Clockworks Signal Processing
    • Epiq Solutions
    • Fidus
    • PalmSens
    • Richardson RFPD
    • Tri-Star Design, Inc.
    • VadaTech
    • Vanteon
    • X-Microwave
    View All
Precision ADCs
  • Data Converters
Precision ADCs
Documents AD7305: Settling time
  • Forums
  • File Uploads
  • FAQs/Docs
  • Members
  • Tags
  • More
  • Cancel
  • +Documents
  • +General: FAQ
  • +AD1139: FAQ
  • +AD1556: FAQ
  • +AD1580: FAQ
  • +AD1582: FAQ
  • +AD2S1200: FAQ
  • +AD2S1205: FAQ
  • +AD2S1210: FAQ
  • +AD2S75: FAQ
  • +AD2S80: FAQ
  • +AD2S80A: FAQ
  • +AD2S82A: FAQ
  • +AD2S83: FAQ
  • +AD2S90: FAQ
  • +AD2S99: FAQ
  • +AD4110-1: FAQ
  • +AD411x: FAQ
  • +AD5940: FAQ
  • +AD598: FAQ
  • +AD650: FAQ
  • +AD652: FAQ
  • +AD654: FAQ
  • +AD7091: FAQ
  • +AD7091r: FAQ
  • +AD711: FAQ
  • +AD7124-4: FAQ
  • +AD7124-8: FAQ
  • +AD7134: FAQ
  • +AD713: FAQ
  • +AD7142: FAQ
  • +AD7147: FAQ
  • +AD7148: FAQ
  • +AD7150: FAQ
  • +AD7151: FAQ
  • +AD7175-2: FAQ
  • +AD7176-2: FAQ
  • +AD7176: FAQ
  • +AD717x: FAQ
  • +AD7190: FAQ
  • +AD7192: FAQ
  • +AD7193: FAQ
  • +AD7195: FAQ
  • +AD719x: FAQ
  • +AD7265: FAQ
  • +AD7266: FAQ
  • +AD7280: FAQ
  • +AD7291: FAQ
  • +AD7298: FAQ
  • -AD7305: FAQ
    • AD7305: Settling time
  • +AD7321: FAQ
  • +AD7323: FAQ
  • +AD7328: FAQ
  • +AD7366-5: FAQ
  • +AD7367: FAQ
  • +AD736ARZ: FAQ
  • +AD737: FAQ
  • +AD7380 : FAQ
  • +AD7398: FAQ
  • +AD7400A: FAQ
  • +AD7401: FAQ
  • +AD7403: FAQ
  • +AD74111: FAQ
  • +AD7415: FAQ
  • +AD7416: FAQ
  • +AD7417: FAQ
  • +AD7418: FAQ
  • +AD7450: FAQ
  • +AD7475: FAQ
  • +AD7484: FAQ
  • +AD7490: FAQ
  • +AD7492: FAQ
  • +AD75019: FAQ
  • +AD7503: FAQ
  • +AD7541A: FAQ
  • +AD7546: FAQ
  • +AD7547: FAQ
  • +AD7568: FAQ
  • +AD7578: FAQ
  • +AD7606-4: FAQ
  • +AD7606: FAQ
  • +AD7606B: FAQ
  • +AD7606C: FAQ
  • +AD7608: FAQ
  • +AD7616 FAQ
  • +AD7616-P: FAQ
  • +AD7621: FAQ
  • +AD7625: FAQ
  • +AD7626: FAQ
  • +AD7631: FAQ
  • +AD7653: FAQ
  • +AD7654: FAQ
  • +AD7655: FAQ
  • +AD7656: FAQ
  • +AD7657-1: FAQ
  • +AD7663: FAQ
  • +AD7674: FAQ
  • +AD7675: FAQ
  • +AD7678: FAQ
  • +AD7682: FAQ
  • +AD7683: FAQ
  • +AD7684: FAQ
  • +AD7685: FAQ
  • +AD7688: FAQ
  • +AD7689: FAQ
  • +AD7690: FAQ
  • +AD7691: FAQ
  • +AD7705: FAQ
  • +AD7706: FAQ
  • +AD7707: FAQ
  • +AD7708: FAQ
  • +AD7709: FAQ
  • +AD7710: FAQ
  • +AD7711A: FAQ
  • +AD7712: FAQ
  • +AD7713: FAQ
  • +AD7714: FAQ
  • +AD7714YN: FAQ
  • +AD7715: FAQ
  • +AD7716: FAQ
  • +AD7718: FAQ
  • +AD7719: FAQ
  • +AD7720: FAQ
  • +AD7722: FAQ
  • +AD7725: FAQ
  • +AD7730: FAQ
  • +AD7731: FAQ
  • +AD7732: FAQ
  • +AD7738: FAQ
  • +AD7740: FAQ
  • +AD7741: FAQ
  • +AD7745: FAQ
  • +AD7746: FAQ
  • +AD7747: FAQ
  • +AD7760: FAQ
  • +AD7763: FAQ
  • +AD7766: FAQ
  • +AD7768: FAQ
  • +AD777x: FAQ
  • +AD7780: FAQ
  • +AD7785: FAQ
  • +AD7787: FAQ
  • +AD7788: FAQ
  • +AD7790: FAQ
  • +AD7792: FAQ
  • +AD7793: FAQ
  • +AD7794: FAQ
  • +AD7795: FAQ
  • +AD7798: FAQ
  • +AD7799: FAQ
  • +AD7805: FAQ
  • +AD7808: FAQ
  • +AD7809: FAQ
  • +AD780: FAQ
  • +AD7811: FAQ
  • +AD7812: FAQ
  • +AD7817: FAQ
  • +AD7819: FAQ
  • +AD7821: FAQ
  • +AD7825: FAQ
  • +AD7829: FAQ
  • +AD7835: FAQ
  • +AD7849: FAQ
  • +AD7851: FAQ
  • +AD7854: FAQ
  • +AD7856: FAQ
  • +AD7858: FAQ
  • +AD7859: FAQ
  • +AD7864: FAQ
  • +AD7865 : FAQ
  • +AD7872: FAQ
  • +AD7874: FAQ
  • +AD7879: FAQ
  • +AD7887: FAQ
  • +AD7888: FAQ
  • +AD7891-1: FAQ
  • +AD7891: FAQ
  • +AD7893-2: FAQ
  • +AD7895: FAQ
  • +AD7896: FAQ
  • +AD7899: FAQ
  • +AD7912: FAQ
  • +AD7921: FAQ
  • +AD7924: FAQ
  • +AD7927: FAQ
  • +AD7938: FAQ
  • +AD7942: FAQ
  • +AD7949: FAQ
  • +AD7960: FAQ
  • +AD7961: FAQ
  • +AD797: FAQ
  • +AD7980: FAQ
  • +AD7982: FAQ
  • +AD7984: FAQ
  • +AD7986: FAQ
  • +AD7988-1: FAQ
  • +AD7993: FAQ
  • +AD7994: FAQ
  • +AD7997: FAQ
  • +AD7998: FAQ
  • +ADA2200: FAQ
  • +ADAS1000: FAQ
  • +ADAS3022: FAQ
  • +ADAS3023: FAQ
  • +ADC: FAQ
  • +ADVFC32: FAQ
  • +EVAL-AD7719-EB: FAQ
  • +EVAL-ADAS3022EDZ: FAQ
  • +RDC1740: FAQ
  • +AD4116: FAQ
  • AD7398 SPI Voltage vs VCC
  • +ADAQ7768-1: FAQ
  • +ADAQ8092 FAQ
  • +DC590, DC2026, QuikEval: FAQs
  • +Legacy LTC - Sigma Delta ADCs FAQ
  • +Precision Technology Learning Modules
  • Programming FMC FRU ID EEPROM on Linux

AD7305: Settling time

Q 

What happens if there are two write cycles with the second cycle done before
the first conversion is achieved ? Is the first cycle interrupted ?
For instance, how is the output if we write 0xFF then 0x00 and then 0xFF in
less than 1 µs ?

 

A 

There are two distinct aspects to consider here; the interface timing and the
settling time of the DAC.

Referring to the interface timing on the AD7305 on fig 4 of the datasheet. The
minimum time required to complete a write to the DAC register is determined by
the setup and hold time of the data, address and load lines: Tsetup + Thold  is
60ns for 5V operation and 90ns for 3V operation. If the setup and hold times
are violated, the data in the input register and/or the DAC register will be
indeterminate.

On the rising edge of /LD data is latched into the DAC register and the DAC
output will start  to slew to it’s new value with a typical slew rate of
3.6V/us. The DAC output is guaranteed to settle within 2us for a full-scale
transition with a 4V reference and 0.1% accuracy (refer to fig 12 for typical
performance). It’s useful to note that the DAC register directly drives the
switches of the internal resistor ladder, the settling time is mainly due to
the output amplifier.

It is not necessary to wait until the DAC output has fully settled before
writing the next value to the DAC register; if the DAC output has not fully
settled before the next /LDAC rising edge, the DAC output will simply slew from
whatever value it is currently at.

In theory you can update the DAC register at a rate of about 10MHz, but large
output transitions will be slew rate and settling limited. Higher DAC update
rates will produce more transition noise and digital feed-through at the output
and degrade AC performance accordingly.

  • ad7305
  • Share
  • History
  • More
  • Cancel
Related
Recommended
Social
Quick Links
  • About ADI
  • ADI Signals+
  • Analog Dialogue
  • Careers
  • Contact us
  • Investor Relations
  • News Room
  • Quality & Reliability
  • Sales & Distribution
  • Incubators
Languages
  • English
  • 简体中文
  • 日本語
myAnalog

Interested in the latest news and articles about ADI products, design tools, training and events?

Go to myAnalog
Analog Logo
©1995 - 2023 Analog Devices, Inc. All Rights Reserved
沪ICP备09046653号-1
  • Sitemap
  • Legal
  • Privacy & Security
  • Privacy Settings
  • Cookie Settings