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AD7450: Sample rate estimation (10MHz) and reference voltage

1. What sample rate is estimated on the AD7450 on a 10MHz clock (driven by the
FPGA limitation)? 

2. What is the minimum voltage reference on the part?  I read the spec as 0.3V
up to VDD on the AD7450A but maybe this can be confirmed for the AD7450 device.


1. A guide on how-to estimate the sampling rate of the AD7450 is given in the
Serial Interface section on page 15 of the datasheet.
The estimation is based on the following two equations for the throughput rate:

(1) troughput rate = t_2 + 12.5 (1/f_sclk) + t_acq

(2) t_acq > 2.5 (1/f_sclk) +t_8 + t_quiet

with  t_8(max) =35ns and f_sclk=10MHz. The quiet time t_quiet is required to be
>25ns and the acquisition time t_acq is required to be >200ns, according to the
With a clock of 10 MHz the acquisition time is >310ns and the requirement is
satisfied easily.

Consequently, the maximum throughput rate for AD7450 at a 10MHz clock amounts to

throughput rate (max) = 636.9kSPS, assuming t_2(min)=10ns.

As this is the best possible throughput rate pushing the specifications to the
limits, I would suggest to leave some margin and expect throughput rates of
600kSPS and below.

2. The minimum reference voltage for AD7450 amounts to 100mV and can range up
to 3.5V for a supply voltage of 5V.
For 3V supplies the minimum reference voltage also amounts to 100mV but can
range up to just 2.2V.

Both reference voltages spans are given in the Notes section below the
Specifications table in the datasheet as well as in the
Reference section on page 14. For your reference I am attaching the screenshots

However, in order to achieve datasheet performance as given in the
Specifications section, a reference voltage of 2.5V+/-1% or 1.25V+/-1% is
required for 5V or 2.5V supplies, respectively.