Q
I have two questions about timing on the AD7475. Hope you can help me.
In the datasheet (Prl 03/00) on page 6, you can read that t4, Data Access Time,
is max 40 ns. T7, Data Valid Hold Time, is min 10 ns.
'Data Valid Hold Time' is 10 ns or more and 'Data Access time' is 40 ns or
less. Does these times depend on each other? If the 'Data Acess time' is long
is the 'Data Valid Hold time' long to?
The max 40 ns for 'Data Access time' is that static? Does it depend on the data
you put in or/and other internal things? Is it some way a user can make that
time shorter than 40 ns (less than the max time)?
A
T4 and t7 are given as max and min specifications. These are the limits to
which the part is tested to. There will be some part to part variation of the
timing parameters but in order to design a reliable digital interface, you must
ensure that the processor can tolerate the minimum data hold time and the
maximum data access time.
'Data Valid Hold Time' is 10 ns or more and 'Data Access time' is 40 ns or
less. Does these times depend on each other? If the 'Data Acess time' is long
is the 'Data Valid Hold time' long to?
If the data hold time is long, then naturally the data access time will
approach it's maximum value. The test program ensures that the data access time
is never greater than 40ns. While there will be some dependency between these
two parameters, YOU CANNOT RELEY ON ANY SUCH RELATIONSHIP. It is absolutely
critical that the interface is designed with the max and min values in mind.
The max 40 ns for 'Data Access time' is that static? Does it depend on the data
you put in or/and other internal things? Is it some way a user can make that
time shorter than 40 ns (less than the max time)?
The data access time will vary from part to part and will also be affected by
capacitive loading. The AD7275 is an ADC. You cannot write data to it. It is
not possible to reduce the data access time.
When interfacing to AD7475 with a fast serial clock, you should clock data into
the processor on the falling edge of SCLK and ensure the processor can accept
the minimum data hold time. If it cannot accept the minimum data hold time, you
will need to use a slower serial clock (80ns period) and clock data in on the
rising edge of SCLK.
