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Documents AD7484: Width of Reset pulse
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    • I am working on a project and am using an AD7484 14bit SAR ADC. The device is running in connection with a FPGA, and later with a CPLD.
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AD7484: Width of Reset pulse

Q 

After reset of AD7484, when  CONVST signal is given by single time, the BUSY is
always low. But when it is given a continuous pulse to CONVST pin, it works
well. I found out that the problem is the RESET signal  provided for the chip
is too short to make it work normally. The specifications you provided on
datasheet dosen't specify how long it is, when I correct it, all is well.

 

A 

A reset pulse is vital to ensure correct operation of the AD7484.  I would
believe that this would fix the issue that the customer previously described.
It is the edge of the reset signal that is used to reset the internals of the
part so the pulse width shouldn't matter too much once it is a reasonable
length (>5ns or so) and happens after the power to the device is stable. Since
the customer didn't provide us with any plots showing the reset pulse widths
before and after the fix, it's difficult to figure out whether it was truly
related to the width of the pulse or the position of the pulse with respect to
the VDD line becoming stable. I agree that a minimum pulse width should be
included in the datasheet though.

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