Thank you for your question but I am having a hard time understanding it. Maybe you could clarify some details. What do you mea by the rise or fall? Is this the clock? and what do you mean hold of 4ns? If you can have a drawing or plots it will be better.
For analog devices,
What is Acquisition Time?
If I have ADC with 100 MHz BW (-3 dB), 350/100 = 3.5 ns rise or fall (10%-90%) time. It's mean at equivalent sampling time i can get 3.5 ns rise time at full scale of ADC. But if I have THA with 5 GHz BW with hold of 4 ns before ADC 100 MHz with 3.5 ns input rise time. So I can see 70 ps rise time at equivalent sampling time. Am I right?
Don't be shy,