There is a unwanted noise coming out from the input pin as the figure shown.
CH1(yellow): BUSY SIGNAL
CH2(cyan): CNVST SIGNAL
CH3(purple): UNWANTED SIGNAL FROM INPUT PIN
This is the natural behavior of the ADC input. On the CONVST falling edge
(cyan), the ADC samples the signal at the input – you can see the glitch on the
input coincident with the falling edge of CONVST. As per the operation of the
AD7653 the ADC then hold with the cap switched in until the conversion is
finished (as indicated by the Busy signal going low). At this point the
conversion is complete and the ADC goes back into track, where the input again
starts to charge the sampling cap to the correct level again. The time from
when BUSY comes low until the next falling edge of the CNVST is then the
acquisition time – it means that during this time the amplifier must settle the
kick from the ADC and charge the ADC internal sampling cap to the correct and
settled value before it is again sampled. Amplifier needs to be in the circuit
– this enables the front end to settle correctly.