Search FAQs on the left to see if your question has been answered. Click on the dropdown to view all of the documents associated with the product. If you can't find your question, click on Ask a Question

AD7682 and AD7688 busy indicator

I am using AD7682 and AD7688 components. I do accesses through a PLD and I am
wondering how using the busy indicator.

In the AD7682 datasheet, in the paragraph "General timing with a busy
indicator", it is written: "At the EOC, if CNV is low, the busy indicator is
As EOC is at the end of tCONV, and tCONV is equal to 2.2 us max, I thought I
had to set CNV high during less than 2.2 us. But when I do board test, there is
a problem, the busy indicator is not generated. Is there something I
misunderstand in the datasheet? Do I have to set CNV high during more than 2.2

With the AD7688, tCONV is defined with min 0.5 us and max 1.6 us. The sentence
in /CS mode 3-wire with busy indicator is "CNV must be returned low before the
minimum conversion time and heldlow until the maximum conversion time to
guarantee the generation of the busy indicator". With the sentence of this
datasheet I understand that I have to set CNV high during less than 0.5 us and
keep it to low until the 1.6 us. Do I misunderstand the datasheet?

I have implemented a communication with the AD7682 and I have observed its
behaviour. Is there a possibility the SDO is not set in high impedance after
the 17th clock cycle?
I have a pull up on SDO and I have observed sometimes a value '1', sometimes a
value '0' on SDO after the protocol, whereas I have set 17 rising edges. I have
joined the chronogrammes with their titles.
Note: the tCNVH has been set to 1 us and the tCK has been set to 5.5 us. tSCK
is equal to 800 ns.


First for the AD7682, to generate a busy indicator on the SDO line, the CNV
signal must be returned low prior to the end of conversion (EOC). The EOC
signal (busy signal) is what we use to determine the conversion time of the
ADC. In busy indicator mode, the busy indicator is generated when a conversion
is complete. The 2.2 uS conversion time that is specified in the data sheet is
a guard banded number that tells you regardless of supply voltage, temperature,
process skew, etc. that the conversion will always be finished within 2.2 uS.
However, the EOC is most likely less than 2.2 uS under normal operating
conditions. Therefore, to enter busy indicator mode, you will most likely need
to bring CNV low well before 2.2 uS has elapsed since a rising edge is observed
on CNV. The guard banded minimum conversion time is actually also specified in
the data sheet and is listed as tDATA. This is the safe data access during
conversion time and is listed as 1.2 uS. This basically says that the part is
still guaranteed to be converting at 1.2 uS after a conversion  is initiated.
So in conclusion, on the AD7682, as long as CNV is brought low prior to tDATA,
the device will enter busy indicator mode and will require an SCLK to clear the
busy indicator before  data is available.

As for the AD7688, the same basic explanation for busy indicator mode that I
just presented for the AD7682 holds true for this device also. The only
difference will be the specific numbers. Instead of having 1.2 uS to bring CNV
low and still enter busy indicator, the AD7688 only provides the user 500 nS.

For our Automatic Test Equipment programs, we use a CNV high time of only 10 nS
(which is the minimum tCNVH time) for entering busy indicator mode and keep CNV
low for the rest of the conversion period.

Another thing you will want to keep in mind is that you should implement and
pull-up resistor on SDO and you will need to provide the 17th falling edge to
place the SDO pin back in high impedance. If you only use 16 falling edges, SDO
will keep the state of the LSB and could potentially stay driven low.

With busy indicator enabled, a total of 17 SCK falling edges are required to
return SDO to high-Z while CNV is low. If CFG readback is enabled, a total of
31 SCK falling edges are required to return SDO to high-Z, so you should see
the SDO high-Z after the 17th SCK falling edge. I'd like to see all four
signals (CNV, SCK, SDO and SDI) on the same scope plot and see how these edges
are lined up.

Did you mean the time between conversions (tcyc) is 5.5µs? Make sure that you
are not violating any of the data sheet timing specifications. There is always
a one deep delay when writing the CFG register. From power-up, in any
read/write mode, the first three conversion results are undefined because a
valid CFG does not take place until the 2nd EOC; thus two dummy conversions are

The AD7682 clocks out bits on the falling edge of SCLK starting with MSB-1, but
you need to wait the tDSDO time before attempting to read a certain bit. The
data can potentially be read on both the rising edge or falling edge of SCLK,
but this obviously depends upon the SCLK frequency that is implemented. In this
case, your SCK is fairly slow- 1.25MHz. For the fastest SCLK rates, it would be
recommended to read the SDO data on the falling edge of SCLK.