work correctly. The Data output is for some input voltages always the same. No
bit toggled. The Timing will the same as in the Data sheet.
AD7683 is a Successive approximation ADC. You may know that a SAR converter
converts by a series of bit trials, deciding the value of the MSB D, then
D, D, D ... down to D. Internally, each bit of a DAC is set,
and the result compared to the Analog input. The result of this comparison
determines the bit value.
One of the prerequisites for a SAR converter is that the Analog input (and the
reference input) remain "constant" for the each bit trial. If you look at
figure 20 of the datasheet , you wil see that the the VREF is connected to the
internal device constatnly while the Signal inputs are disconnected during the
If one of the bits is incorrectly set (e.g. bit 6 is set to a 1 when it should
have been a 0, due to a noise spike during that bit trial) then all of the
following bits will be set to either all "0" or all "1", to try to reduce the
DAC output to the correct value.
The sample and hold at the Analog input ensures that the Analog input to the
ADC remains constant during the conversion. However, there is no sample and
hold at the reference input. Indeed the Vref pin is a dynamic load for the
amplifier or reference that is driving the pin - as stated in the datasheet
For this reason a Capacitor of 10uF or greater , right at the inputs of the
VREF is required to keep the VREF inputs noise free during conversion. So
ensure this CAP is there and ensure that a low impedance reference is used for