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I'm trying to use an AD7705 with a 87LPC768 microcontroler with the signals DIN and DOUT wired together and pulled-up to 5V with a 10k resistor and I can't make it work even if it is the same schematic I found in your datasheet. Can you help me ?? Is there anything special to do ??
It is possible that the digital interface is getting out of sync, when using the digital interface of the AD7705, it is critical that you provide the correct number of clock cycles when reading from or writing to the control registers. If you provide one extra clock cycle and then write to the part, you will put the part into an unexpected state. Similarly if you are reading from a 24bit register and you only provide 20 clock cycles, the interface will be out of synchronization. One possible cause is spurious clocks on the SCLK line. The interface expects the first bit of any write to be a zero. If the first bit is a one, it will ignore all writes until it sees a zero. If after performing a read, you leave DIN low, any spurious clocks on the SCLK line will clock a bit into the comms register. The next time you write eight bits to the comms register, onty the first seven bits will be loaded and the eigth bit will be interpreted as the first bit of a subsequent write. You can avoid this problem by pulling DIN high after each write. If you are using the /CS line as a Frame Sync, check that this line is brought high at the correct time. Check that you have allowed the correct number of clock pulses to occur before /CS is brough high. You can reset the digital interface at any time by writing 32 logic 1s to the comms register. As some microprocessors share a single DATA OUT and DATA IN lines as in your application, a single10K pull-up resistor is used on this single data line. In this case if the interface gets lost, because the read and write operations share the same line, the procedure to reset it back to a known state are somewhat different than previously described. It requires a read operation of 24 serial clocks followed by a write operation where a logic 1 is written for at least 32 serial clock cycles to ensure the serial interface is back to a known state.