The ADC data is stable during a time period after every SCLK falling edge. The DOUT data is not known immediately at SCLK falling edge; it requires up to 23ns for conversion. During that time period (at SCLK = 48MHz), there is a second SCLK falling edge that is requesting the next bit. The internal circuitry is complex but has multiple stages, so that one bit is being determined while the next bit is being requested.