Interface. (500 KHz clock speed)
I use a CMOS source with a 2.0 MHz clock
According to the manual I tried to init the AD7706 for an update rate between
20Hz and 400 Hz.
After starting the conversion, run a self calibration and monitor the DRDY pin
I receive only a few (1 .. 5) falling edges. After that there is no further
activity on the DRDY line. Which terminate my polled interface.
This canâ€t be the right way! Since the AD7706 is sampling the input with
FSYNC LOW in the setup register
I used the example code printed in the manual and got exactly the same behavior!
SO what am I missing here.
The first thing to check here is the use of the digital interface. When using
the digital interface of the AD7705, it is critical that you provide the
correct number of clock cycles when reading from or writing to the control
registers. If you provide one extra clock cycle and then write to the part, you
will put the part into an unexpected state. Similarly if you are reading from a
24bit register and you only provide 20 clock cycles, the interface Will be out
One possible cause is spurious clocks on the SCLK line. The interface expects
the first bit of any write to be zero. If the first bit is a one, it will
ignore all writes until it sees a zero. If after performing a read, you leave
DIN low, any spurious clocks on the SCLK line will clock a bit into the comms
register. The next time you write eight bits to the comms register, only the
first seven bits will be loaded and the eighth bit will be interpreted as the
first bit of a subsequent write. You can avoid that problem by pulling DIN high
after each read.
If you are using the /CS line as a Frame Sync, check that this line is brought
high at the correct time. Check that you have allowed the correct number of
clock pulses to occur before /CS is brought high. You can reset the digital
interface at any time by writing 32 logic 1s to the comms register.
The following conditions could prevent the /DRDY line from updating.
• The /RESET is pulled low
• The FSYNC bit is set
• The STBY bit is set
• The /DRDY pin is pulled low externally
Check that the analog input voltage applied is within the common mode voltage
range, in buffered mode you must ensure that the input is within the common
mode range GND+50mV to Vdd-1.5V. For testing, I recommend tie all channels to
the reference (2.5V). The output code should be close to mid-scale.
Be aware that when you change channels on the AD7705 you have to wait the
required settling time before you read out a result. This is four times the
normal update rate. If you always wait for /DRDY to go low before reading from
the data register, you should not have any problems.
Here is a good procedure for debugging the serial interface:
1)Power up the part and execute a RESET to ensure everything is in it's default
2)Next try to read from the setup, gain and offset registers and check that you
can read back the power on default values as given in the datasheet.
3)Now try writing to the communications register selecting channel 1.
4)Immediately execute a read from the communications register and compare the
received channel bits with the ones you wrote.
5)Do the same operation for channel 2/
6)If you don't get back what you write to the channel bits, you need to look
carefully at the digital interface and your software for possible framing