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AD7707:input impedance and currents

I´ve got some questions about the specifications of the AD7707. I´m working
actually with the low level inputs. I didn´t found clearly values about the
input impedance or input currents in buffered or unbuffered mode in the data
sheet. Could it be that, in unbuffered mode with gain 16, the input current
is in the range of 1uA? This is what I observed. I think you will have a
data sheet in more detail and you will be able to provide me with this


The thing that concerns me about your system is that the 1nF capacitors between
the low level inputs and ground continue to give rise to dynamic currents even
when the part is operating in buffered mode. It is certainly a risky strategy
to operate the part without any anti-aliasing filter at all but if you have
filtering earlier in the signal chain then you can perhaps leave the capacitors

To explain the dynamic current problem, which should only happen in unbuffered
mode, I attach a plot which I did for the AD7712, which also has unbuffered
inputs. I'll try and explain what the plot tells us:
Firstly, the unbuffered input stage of sigma delta converters is a sampling
capacitor of a few pF which is switched between the Ain+ and Ain- channels (in
this case Ain1 and LOCOM). Charge is transferred onto the sampling capacitor
from Ain+ and then charge is transferred off the sampling capacitor to Ain-. To
make the simulation easier, I just model what happens when the sampling
capacitor starts off being charged to 2.5V and an external capaitor starts off
being charged to 0.2V. At t=0, the sampling capacitor is connected to the
external circuit. The sampling capacitor, C2 loses most of it's charge to the
external filter capacitor through R2, as we would expect. Because C1 is much
bigger than C2, the voltage increase in C1 (about 1.8mV) is much smaller than
the voltage decrease in C2 (-2.3V). However, the interesting thing is the
charging time. The sampling capacitor gives up it's charge to the external
capacitor very quickly. However, the external filter capacitor takes a much
longer time to discharge back to 200mV. It is this long time constant which
causes the a gain error in the ADC result. The settling time of the input
voltage is made much longer by the external passive components and has not
settled by the time the conversion takes place, leading to the error. The
numbers in this example aren't correct for the AD7707 but they demonstrate the

To choose a value of capacitor, the table XVI on page 20 is the first guide.
Note that the "time constant" (t = RxC) represented by the R and C combinations
is related to the input sampling frequency T at any particular gain, which is
shown in table XVII on the following page. It turns out that RC = T/7 for the
50pF value of capacitor but only T/2.5 for the 5nF capacitor.

The combination of the two tables is in the attached spreadsheet.

Here is the text of the email which I wrote to another customer, who was
experiencing difficulty with the dynamic input of a sigma delta converter, in
this case on the ADuC824 microconverter.
"The reason for the R and C on Ain1 and Ain2 inputs is as a simple
anti-aliasing filter, to prevent noise at high frequencies being aliased down
into the pass band. The internal buffer means that the R, C circuit doesn't
cause gain errors in the reading. The high oversampling ratio of the ADC means
that a single pole anti-aliasing filter is usually sufficient, even when there
is a lot of out-of -band signal, which needs to be attenuated.

To drive the auxiliary channel from the signal you describe, with such a high
source impedance, you have to buffer the signal so that the bias current drawn
by the ADC (and any dynamic current) doesn't cause a gain error, because of the
voltage drop across the 5k source impedance. You may also have to implement an
anti-aliasing filter, to band-limit the input signal depending on how much
noise is present in the input signal and what your noise requirements are for
the auxiliary channel. For example, if your 2V signal has a lot of out-of-band
noise, this noise will be aliased down to baseband and will appear as low
frequency fluctuations in the sampled result, even though the original noise
may have been at several hundred kHz. The noise may be induced into the analog
inputs from adjacent signals, hf radiation or it may be generated in the buffer
amplifier itself.

Therefore I recomend that you drive the Auxiliary channel with a unity gain
buffer, followed by a single pole RC filter to prevent aliasing.

One note of caution I have to mention: since you cannot use large values of R
and C at the front end of an unbuffered sigma delta converter without causing a
gain error, the anti-aliasing circuit cannot really have a cutoff frequency
below 15kHz (2.2kOhms and 4.7nF) if gain errors are to be avoided. I have taken
these figures from the AD7714 datasheet, on which the ADuC824's primary ADC is
based. Since the ADuC824 has not yet been released, there is no information on
the datasheet, but I would expect a similar type of limitation to apply to the
ADuC824 as applies to the AD7714 in unbuffered mode.

Since there is a tradeoff between
a) cutoff frequency of the low pass anti-aliasing filter
b) gain error caused by the RC filter,
you cannot optimise both of these by choosing values of R and C.

Some suggestions are
a) use higher values of R and C, accept that there will be a gain error and
calibrate it out in the ADC
b) use low values of R and C to minimise the gain error, and use a low noise
op-amp (e.g. OP113) to minimise the aliased noise
c) use an OP213 (dual op113), with the first stage buffering the 5k source
impedance and the second stage buffering an RC anti aliasing filter and driving
the ADC directly.