Is it possible to apply a clock higher than the specified 32.768kHz? How far a
variation does the PLL support, and how does the noise performance evolve? Any
data you could have?
The AD7709 is intended for use with a 32.768KHz watch crystal. The PLL
internally locks on to a multiple of the 32.768KHz watch crystal frequency to
provide a stable 4.194304 MHz clock for the ADC. The absolute accuracy and
temperature drift of the clock source is important since the output update rate
and placement of filter notches is a direct function of the clock frequency.