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AD7712: Master clock

I would like to use sigma-delta converters for a
multi-channel (48) acquisition application. There
is a stringent need for synchronicity between
each converter in our application.

I am interested in using AD7712 converters since
it features multi-channel acquisition capabilities:
the SYNC pin can be turned low "to reset the
nodes of the digital filter" (I quote the
datasheet), and consequently to synchronise
number of ADCs.

Assuming that we drive the bunch of ADCs with a
single 10 MHz clock, and that we synchronize the
ADCs with a single SYNC pulse signal, what are
the typical and maximum skews between the DRDY
signals one can expect: within a 10 MHz clock
period, a few micro-seconds, more ?


You are correct, if you drive multiple AD7712s from the same master clock ( and
ensure the master clock is properly distributed to avoid clock skew between
ADCs) you can use the SYNC pin or SYCN bit to syncronise multiple ADCs. This
will ensure that sampling of two or more sycnronised ADCs happens
simultaneously (within 100ns) and that the output DRDY occurs at the same time
for all devices.

Do note that the AD7712 is a sigma delta device and therefore there is a
latency of 3 conversion periods between releasing the SYNC pin and the first
conversion result being available. Similarly, if you apply a step change to the
input of the AD7712, there is a latency of 3 conversion periods before the
result is valid. See note on page 10 under "Filter Section"
The AD7712 is a mature product and w have since moved to our third generation
of sigma delta products (lower power, lower cost, more functionality). For new
designs I would recommend the AD7705/06 for low cost 16bit measurements, the
AD7707 if you require a high level input and the AD7714 for 24bit resolution.

In addition, if you do not require simultaneous sampling of all 48 channels,
consider the AD7718 and AD7708 which have an on chip 8/10channel MUX.