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In our application, some AD7712 use System Offset Calibration initiated, after the power-up, together with the device configuration, by the means of a single writing of the Configuration Register (0x8297A1). In our case, the calibration duration is about 900 milliseconds. Some tests show that, once started, the calibration process may be interrupted by some accesses to the ADC registers (for instance reading of the calibration registers) before the end of the calibration (DRDY). In this case, the calibration registers contents remains unchanged. Do you have knowledge of others operations having as consequences to interrupt the calibration process ? In our application, from time to time, some ADC doesn't process correctly the System Offset Calibration for undeterminate and not reproducibled reason. Our customers (Alcatel Alenia Space and European Space Agency) are worried to know if such anomaly may be the sign a the degradation or failure of the part.
You can start a calibration process at any time. This will interrupt the process at any time. The pins labelled TFS and RFS are used to control writing to and reading from the part. These pins should be pulled high via a pull-up resistor when not in use or when you want to ensure that the part is not inadvertedly written to or read from, We advise that SCLK is kept low between read/write cycles as it is the falling edge of SCLK that clocks out the data and the high level, that clocks in the data, therefore if the SCLK is kept low between read/write operations you have less chance of spurious clocks affecting the operation, wheras if SCLK is high between read/write operations, noise on the line may be interpreted as a falling edge/valid clock high pulse. In addition: The signals TFS and RFS gate the SCLK and SDATA, if you keep these signals high while using the SCLK and SDATA to communicate with other devices you will not affect the AD7712.