You can use a port pin to drive the PLL, the frequency needs to be 32kHz. The
PLL circuit operates over a wide tolerance >+/-20%. Clock jitter on the clock
is not critical in most sigma delta ADC; the high oversampling ratio and
decimation effectively eliminate any error due to clock jitter.
However, frequency drift over time and temperature can be critical. Any change
in the input clock will directly influence the output update rate, position of
the notch in the digital filter and cutoff frequency. SO you should ensure that
frequency drift is minimized.
One further point is that the AD7719 expects to be drive from a continuous
clock source. Use the power down options to minimise power consumption, don’t
be tempted to stop the clock .