circuitry just as in Data Sheet (rev. 0, p.19, figures 39-40). The design
requires a simultaneous and synchronous working of both of ADCs. Is it
possible in this master-slave configuration? The problem is: FSI input of
the slave ADC is triggered by FSO output of master, which controlled by an
external FSI. I wonder if start sampling points (time reference) will be
the same for both ADCs or they will be 32(64) CLK shifted? Would you also
give some explanations of the difference between FSI and SYNC effect
concerning this circuit.
1. Is it true that the FSI pin is used to synchronize the 2 ADCs,
meaning that analog input signals of the master and the slave are
sampled at the same time ?
Yes. The FSI pin is used to synchronise the filters when two AD7723s are used
in a system. The two devices will sample at the same time. The master will
start to output its data immediately and the slave will start to output it's
data 16 clock cycles later (when FSI for the slave device goes high). Using
this scheme, two AD7723s can share the same serial bus.
2. What is the advantage to asserts FSI periodicaly every 32 CLKIN
instead of applying it once after power-up, specially if the CLKIN of
the 2 converters are the same?
To be honest there is no need to assert FSI(master) every 32 clock cycles, you
only need to do it once after power up. Some customers, however, are more
comfortable asserting FSI every 32 clock cycles. I think it gives them a "warm
fuzzy" feeling to know that the devices are being continually synchronised. You
are right, there is no need for this.
3. Because FSI seems to interrupt the internal conversion and restart
the digital filter, what is the time delay (nbr of CLKIN periods)
between FSI and first available data ?
Page 2 of the data sheet gives the settling time for the digital filter. This
is also the time between synchronising the part and getting a valid output from
it. I'll check and get confirmation of these numbers.
4. What is the purpose of the SYNC pin compared to the FSI pin in the
serial mode 1 ?
The first time it is asserted, FSI will synchronise the two devices. On
subsequent assertions it is more or less ignored. The SYNCH input will cause
the digital filter to flush and the part to synchronise whenever it is
asserted. Therefore SYNCH can be used to resynchronise a device.
5. In the Fig.39 application , the FSO pin of master ADC indicates which
ADCs is currently providing the data (Master or Slave): True or Not ?
True. You can use the FSO(master) pin to indicate which ADC is currently
6. In Fig 39, are the data from the Master and then the data from the
slave correponding to input signals sampled at the same time or is there
a 16 Clkin periods delay between the 2 sampled instant ?
Same as Q1. The data is sampled at the same time. The slave device delays
outputting it's data for 16 clock cycles