Q
I have to realize an A/D board with four ADCs (AD7730). The input
signals are in 0-10 mV range, and I need at least 14 bits of resolution
or greater. I have built an evaluation board to test converters'
performance, but I am not satisfied. I have noted that the sclk
signal is very critical and the adc introduce a lot of noise (I
have only 10 bits of resolution). Nevertheless I think that the
problem is my demo-board and not adc part. 1) Could you send
me any information about AD7730, layout and routing circuit problems
? 2) How can I reduce adc's noise effects ? 3) How can I deliver
sclk signal to four adcs ? 4) Is it usefull amplifing and filtering
input signal to reach max adc input range ?
A
To properly specify the expected resolution of the AD7730, you must need to
quote, the input range you are using, output update rate and the status of the
CH=P BUF and BIPLOAR bits.
You can then refer to the noise tables on pages 10 and 11 of the datasheet to
determine the expected noise performance and resolution. For example for a
0-10mV input range with a 50Hz update rate, you can expect a peak to peak
resolution in excess of 15bits. However, if you set the update rate to 1200Hz,
the peak to peak resolution will only be 13.5bits.
I would tend to agree with your assessment that the most likely cause is the
layout of your PCB. The device noise of the AD7730 is of the order of 160nV rms
provided the bandwidth is kept low by keeping the output update rate low. As
you increase the bandwidth, more device noise will be present in the output and
eventually as you increase the bandwidth further, the quantisation noise of the
conversion process will start to dominate and the resolution will fall off
drastically.
1) We have an evaluation board available for the AD7730, details are given on
our website. The eval board shows the recommended layout for a single AD7730. A
few notes on grounding for sigma delta converters follow:
The pin marked DGND on the AD7731 is the return path for the digital current
out of the AD7731. It does not necessarily mean that this pin should be
connected to the digital ground plane of your system.
Connect the AGND pin and the DGND pins of each individual IC together with a
broad, low inductance track. You can now treat each of these seven nodes as a
single analog ground connection to be routed onto your system analog ground
plane. You should provide a separate ground return path back to the power
supply for each converter in the system. If each AD7730 has 7mA of analog
current and 1mA digital, providing separate return paths means that there is
only ever 1mA digital current in each converters local ground plane. You can do
this by flooding the analog ground plane and sectioning it off with cuts to
provide a local ground return path for each converter. The digital current from
the AD7731 is relatively small in comparison to the analog current and provided
you use low inductance ground paths this small amount of digital current
should not adversely affect the noise floor.
You should ensure that AVDD is decoupled to AGND and DVDD is decoupled to DGND.
The system analog ground plane should be kept separate from the system digital
ground plane, which routes the return current for the “spikey”, digital
components such as micro-controller, digital buffers, logic etc.
The connection between the system digital ground and system analog ground
should be made at a single point (commonly referred to as the “star point”).
Where you place the star point will depend on your system but this is often
determined by the power supply you use. The single connection between analog
and digital ground is already made at the power supply. Your job as a designer
is to ensure that no digital current is allowed to flow in the analog ground
plane while ensuring that the potential of the analog and digital grounds in
your system remain equal.
The final chapter in all our seminar books is dedicated to hardware design
techniques and deals with such issues as grounding, decoupling, parasitic
thermocouples and good PCB design.
http://www.analog.com/support/standard_linear/seminar_material/index.html
2) The ADC is not inherently noisy. As described above the noise in the ADC is
a trade off between update rate and resolution required. If you have noise in
your system which is limiting the peak to peak resolution to 10bits, this could
be due noise or spurious signals on the inputs, a noisy power supply ( if you
have a switched DC DC converter in your power supply, this can generate a lot
of noise), or it could be due to poor grounding in the system which allows high
frequency digital currents to move the ground potential around.
3) The SCLK is not related to the master clock frequency in any way. You should
have a separate crystal supplying the master clock to each ADC. Your system
should then read each ADC in response to DRDY going low. You can only address
one ADC at a time therefore the delivery of SCLK to all four ADCs should not be
critical. Where you might have an issue is if SCLK is not shielded and can
couple into the input or the power supply (or both). When tracking SCLK around
your system, ensure that you have ground below at all times and ground on both
sides of the SCLK track. Look for places in your PCB where SCLK could couple
onto other lines.
4) Amplifying an input signal which starts in the 10mV range will almost
certainly add more noise into the signal of interest. Most opamps will be
dominated by 1/f noise, and generally in sensors it's the low frequency
information you are interested in. Designing a pre-amp will be a very difficult
design job. I would suggest that interfacing directly to the AD7730 with a
single RC anti-alias filter will yield the best results in the shortest time.
Once you can get the AD7730 operating correctly you should be able to achieve
up to 16 bit peak to peak resolution.
