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Table of Contents
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  • +General: FAQ
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  • -AD7730: FAQ
    • AD7730: Calibration Coefficient
    • AD7730: Load cell
    • AD7730: Matching between different gain steps/stages
    • AD7730: Evaluation board
    • ADC for low range pressure transducer
    • AD7730: Increase in resolution
    • AD7730: Required capacitance across the XTAL/ Resonator
    • AD7730: Parallel port of the PC
    • AD7730: Using the chop mode
    • AD7730: Maximum ratings
    • AD7730 Replacement - AD7195
    • AD7730: ESD protection
    • AD7730: RDY signal not working
    • AD7730 Internal-zero-scale calibration
    • Single Micrel FET MIC4427 driver
    • AD7730: When /CS is high, is DOUT is in tri-state mode
    • AD7730 application question re 6-wire loadcell
    • AD7730
    • AD7730: Can't get 24-bit resolution
    • Noise when switching from chop to non-chop mode
    • Only achieving 10-bits of stable resolution, should be 13-bits or more
    • Problems initiating calibration on AD7730
    • We’ve been using the AD7730 for years without any issues. However, after redesigning the PCB—using the same hardware and software but in a more compact layout—we're seeing ADC drift. What could be causing this change?
  • +AD7731: FAQ
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AD7730: Matching between different gain steps/stages

Question

There was at least one important question left: How good is the matching
between the different gain steps/stages (1,2,4,.. etc.) of the PGA for example
in the 7730 or 7714.

Concerning this topic you talked about some kind of application notes about how
to calibrate mV inputs using the PGA with higher gain when only having a 2,5 V
Reference for full scale calibration. Could you please send this information to
me ?

Answer

The answer to your question is "it depends". It's different for the AD7730 and
AD7714 and depends on whether you use the AD7730 in Chop mode or not. I have
included a presentation which takes the form of Frequently Asked Questions.
It's not really an app note but there's a lot of useful information in there.
If this doesn't answer your specific question, let me know.

In addition, many designers want to use the AD7730 with input ranges other than
those given in the datasheet, for example if there's a requirement for a 60mV
full-scale. The notes below explain how you can adjust the calibration
registers directly for different full-scale ranges and to subtract known
(static) bridge offsets.

" There are a couple of ways that the designer can approach this problem. The
first and simplest is to do a system offset cal and a system fullscale ca on
the device for his offset and fullscale conditions.
The second method is to adjust the calibration coefficients in the part for the
desired operation The following details how this can be achieve, examples are
attached.

To adjust the offset register the following needs to be done.

1. Perform a self gain calibration (This will corrupt the Offset Register)
The purpose of this is to adjust for the actual gain of the part, which is
nominally 31.25 on the 80mV range.

2. Perform a self offset calibration. For CHP=1 this will be close to 800000


For the 80mV range, 1 Offset Register LSB corresponds to 13.2975nV, assuming a
gain of exactly 31.25, and the correct reference is used (2.5V with Hiref=0 or
5V with Hiref=1). This nominal LSB needs to be scaled to correct for the part's
actual gain and the actual reference used.

1LSB = 13.2975E-9 * VREF * Actual Gain Register
--------------------------------------------
VREFnom * Default Gain Register VREFnom=2.5Vor5V

This should then be scaled depending on the range, e.g. divide by 8 for 10mV
Range.

The code to be added/subtracted to/from the offset register is then determined
by dividing the external offset to be removed by the LSB calculated.

Therefore, assuming a gain of 31.25, and a default reference, then if an
external offset of 10mV is to be subtracted, 752021(decimal) should be added to
the offset register result obtained to produce 8B7995(Hex). If an external
offset of 10mV is to be added, 74866B(Hex) should be written
to the offset register.

If the DAC is being used, the above calculations would change, however given
that the DAC does not subtract a precisely defined offset, it is not likely to
be used in conjunction with the above method.

The gain register is simpler to manipulate for system full-scale. The procedure
here is to:
1. Perform an internal gain cal
2. Perform an internal offset cal (To correct corrupted offset register)

The gain coefficient produced in 1 is then simply scaled by multiplying it by
the default Full Scale for the selected range, divided by the system full scale
analog input, then corrected for the actual reference:
Adjusted Gain Reg = Initial Gain Reg * VREF * Nominal Full Scale Input
-----------------------------------------------------
VREFnom * System Full Scale Input

E.g. If the maximum analog input is 60mV, then for a 60mV input to produce
FFFFFF on the 80mV range, the gain coefficient should be multiplied by 80/60.

This system full scale input is the input after any offset has been removed by
the DAC or offset register.

If adjusting of both the offset and gain registers is required in the manner
described above, then the offset register should be adjusted first, and the
gain coefficient obtained in step 1 scaled as above.

-------------------------------------------------------------------------

Here's a few more complicated examples of adjusting the Offset Register. They
all assume the 80mV range is selected, and an external 10mV offset is to be
removed.

I. Vref = 5, Hiref = 1, CHP = 1, Gain = 31.25 (Same example as previously)
1. Gain Cal -> 593CEA
2. Offset Cal -> 800000

13.2975E-9 * 5.0 * 593CEA
1LSB = ------------------------- = 13.2975nV
5.0 * 593CEA

Code = 10mV / 13.2975nV = 752021 Dec [b7993 Hex]
=> Offset Register = 87b993


II. Vref = 4.5, Hiref = 1, CHP = 1, Gain = 31.25
1. Gain Cal -> 593CEA
2. Offset Cal -> 800000

13.2975E-9 * 4.5 * 593CEA
1LSB = ------------------------- = 11.98775nV
5.0 * 593CEA
Code = 10mV / 11.98775nV = 835578 Dec [cbffa Hex]
=> Offset Register = 8cbffa


III. Vref = 4.5, Hiref = 1, CHP = 1, Gain = 34.375 (X 1.1)
1. Gain Cal -> 5120A1
2. Offset Cal -> 800000

13.2975E-9 * 4.5 * 5120A1
1LSB = ------------------------- = 10.88nV
5.0 * 593CEA
Code = 10mV / 10.88nV = 919114 Dec [e064a Hex]
=> Offset Register = 8e064a
(The actual gain will never be that far from the ideal)


IV. Vref = 4.5, Hiref=1, CHP=0(Inherent Offset of ~2mV), Gain = 34.375 (X1.1)
1. Gain Cal -> 5120A1
2. Offset Cal -> 7D31E3

13.2975E-9 * 4.5 * 5120A1
1LSB = ------------------------- = 10.88nV
5.0 * 593CEA
Code = 10mV / 10.88nV = 919114 Dec [e064a Hex]
=> Offset Register = 7D31E3 + E064A = 8b382d
"

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