Please refer to Data Sheet Rev. 0 page 4. table: Timing Spec. What is the meaning of t9: will the DOUT be tristated 10 to 80 ns after SCLK rising edge sampling LSB, no matter if -CS is kept low? (t9 is referred to SCLK, not -CS) Does it apply only to LSB, or DOUT is tristated t9 after each SCLK rising edge? NEXT PROBLEM: t6+t7=100ns. Could I use 10MHz SCLK, and as t5=0..60ns, I can not be sure of sampling by rising edge, so I would use falling edge?
Q1: The DOUT is an active logic output only during the read operation, i.e., during the time the data are being shifted out. For the rest, the DOUT is tri-stated, regardless on CS. Therefore, the t9 is correctly related to the last SCLK corresponding to the LSB in the read operation, i.e., to the 8th bit when reading an 8-bit register, 16th bit when reading a 16-bit register, etc. Q2: The t5 max of 60ns is specified with 50pF load on the digital output. The load is usually less - and the max time should be shorter for lower capacitive load. In my setup - AD7738 DOUT driving a standard ADuC824 digital input + 15pF oscilloscope probe, room temperature, the t5 is typically 20ns. Therefore, I believe the AD7738 should work with 10MHz SCLK, just keep the digital signal capacitance to ground low (short tracks on PCB, low number of digital inputs connected to the signal.)