Q
I am using an AD7790 adc for the analog input stage after an instrumentation
amplifier. It is used for a digital sensor.
Please write your questions or comments here: Our design now basically works
okay but sometimes after powerup we get totally incorrect values from the ADC
(one constant value, upper or lower bound). After power cycling the target a
few times the results are correct (there are no changes in the software). On
powerup the software currently only performs a reset of the adc (32 continous
1s) and then starts to read its values. Are there any special considerations to
take care of during powerup?
A
Your information below implies that you are using the default values of the
internal registers in the AD7790.I would expect that after power on, the serial
interface is RESET and expects to see a write to its communication register,in
default conditions, the device is placed in continuous conversion mode, so you
should see the RDY cycling low at the default datarate.
Otherwise, here are a few notes which may help in solving the issue.
The SPI interface can be particularly sensitive to interfering noise.
The most likely reason for reading incorrect data from the AD7790 registers is
an extra spurious (extra) clock pulse appearing on the SCLK line.
The CS line does synchronise the writing of data, but if an incorrect number of
data bits are written then the interface could get confused, and will not
recover when the next time CS is asserted.
The way to reset the interface when communication has been lost is to take Din
high and put in 32 SCLK cycles to the part.
If you have established proper communication between the AD7793 and your micro,
you should be able to read back the contents of the registers that you have
programmed. Is that possible?
If you cannot, then you will need to verify your code by connecting a scope to
SCLK, DIN of the ADC to verify that the correct information is being sent to
the ADC as per fig 3 and fig4.
Try putting a small value cap from the SCLK pin to AGND.
If a capacitor on the SCLK fixes the problem, then it is likely that you have
excess noise on your board. The transistors that make up the serial interface
are actually quite fast and can react to high frequency noise/interference.
Noise
- If the SCLK is very noisy and has multiple transistions on each clock edge,
then the same databit will be input or output several times which will cause
the ADC and the controller to lose synchronisation. The capacitor ( possible 15
to 30Pf) isn't a very satisfactory solution. Better solution is to solve the
noise problem.
Overshoot/ringing
- If the clock edges are very fast, and the SCLK line is quite long then you
can get overshoot/ringing, reflections, etc causing false transitions on the
line. A little extra capacitance can help to lower the bandwidth of the line,
but again this is not an idea solution. Series resistor is a better solution.