2) can you confirm the bit order for reading and writing with SPI. is it MSB
1. With reference to the AD7817 datasheet, page 5, the maximum clock speed is
SCLK at 12.5MHz. This is based on t8 and t9, the minimum low pulsewidth and
minimum high pulsewidth for the SCLK signal. 40ns + 40ns => minimum SCLK period
of 80ns, which corresponds to maximum SCLK frequency of 12.5MHz. The datasheet
gives no specification for the minimum period of SCLK and I therefore assume
minimum period = minimum low time + minimum high time
Some other products quote three clock specifications, minimum period, minimum
low time and minimum high time. This is done to establish maximum and minimum
clock duty cycle allowed.
However, the AD7817 is not specified in this way. The serial interface
operation is guaranteed with as long as you respect the minimum low and high
times. (i.e. from 0Hz up to 12.5MHz with 50% duty cycle, or up to a lower
frequency with another duty cycle, as long as the minimum SCLK low and high
times are respected)
You should consider the maximum sampling rate (you have to be able to clock all
the sampled data out in time), and the requirements of your microprocessor/ASIC
when chosing the clock frequency, but otherwise, keep the SCLK frequency as low
as possible to minimise power dissipation and EMI emissions.
2. Again with reference to the AD7817 datasheet, page 15, figure 20, the
transfers are shown MSB first. Don't be confused by figures 16 and 17; the
description of the Din and Dout lines is just shorthand, and the correct order
is shown on figure 20.
You have the option of only clocking out the first 8 MSBs of conversion data
(DB9~DB2 or should that be DB7~DB0), and then toggling RD/WR- low to discard
the remaining LSBs from the serial interface.