in direct requence (double function of signal necessary) ? The second pulse
will follow the first directly (100ns pulse width )
A conversion is triggered off the rising edge of convst, once started that is
it until the selected conversion sequence is complete. Any further convst edges
are ignored. So logically it will be ok to have a second convst directly after
the first, but there is a risk of effecting the conversion accuracy if the
pulse edges occur at critical times. Some notes we have indicate that the first
critical position would be around 170ns after the first convst rising edge, but
that is just a very rough guide. Have you considered gating out the second
convst, possibly with the Busy signal?
I have assumed the part is operating in internal clk mode, if the conversion is
being clocked with an external clock then clocking after the second convst
signal would be the thing to do.