tell me the maximum fsclk = 2 MHz, but I cannot find a spec for minimum fsclk.
2. What secret is behind the minimum spec for SCLK High Pulse width = 0.4 tsclk
and for SCLK Low Pulse width = 0.4 tsclk. Why the factor 0.4 ?
1) The SCLK is also used for the internal bit comparisons.
In order to avoid capacitor droop, we recommend that the SCLK timing must be
fast enough, such that the conversion time is not less than 50usec.
This would mean that SCLK should be greater than (1/tconvert ) x 16 = 320Khz.
2) The 0.4 factor relates to keeping the mark-space ratio above 40%.
If you look at footnote 2 in the notes below the Timing Specifications Table
you will see it mentions "Mark/Space ratio for the SCLK input is 40/60 to
60/40. See Serial Interface section."
The Serial Interface section is on page 13 of the datasheet.