May I read data for two 8-bit cycles?
The SCLK for the AD7888 is also used for the internal bit comparisons...
In order to avoid capacitor droop, we strongly recommend that the SCLK timing
must be fast enough, such that the conversion time is not less than 50usec (
period that CS is low).
This would mean that SCLK should be greater than (1/tconvert ) x 16 = 320Khz.
Refer to fig 13 of the datasheet, CS should be kept low for the duration of the
two 8 bit reads, SCLK should idle high between the two 8 bit reads.