The AD7768/AD7768-4 MCLK can be applied by using one of the three different options that are available to the user. The purpose of this document is to further explain these three options and how they are configured. The three options are: external CMOS clock, crystal oscillator or LVDS clock.
The initial power up of the AD7768/AD7768-4 uses an internal oscillator to set up the device. The clock control is then transferred to an external clock which is valid between 1.15 MHz and 32 MHz. (The maximum crystal frequency from the datasheet is 34 MHz) If the externally applied clock is not detected or an error occurs, then the Device Status register (Register 0x09) will log this error by setting the clock error bit to a one.
To select the CMOS clock option the following conditions must be met:
In order to use an external crystal it is necessary to adhere to the following steps:
The LVDS clock option is available only in SPI control mode. The following steps must be carried out to enable LVDS clocking to be used:
For further information please consult the product datasheet.
The AD7768/AD7768-4 evaluation boards allow the user the option to set the MCLK to one of the three options discussed above. The CMOS clock is enabled on these evaluation boards by default. For more information please see the products' evaluation board web page.
EVAL-AD7768 Evaluation Board | Analog Devices
Since the updated datasheet is not yet available, I have a question about setting the FILTER/GPIO4 pin for crystal/LVDS mode selection - should that pin be programmed as GPIO output (required level set…
There are two scenarios here and both can be used to enable the LVDS clock option in SPI mode:
Since the updated datasheet is not yet available, I have a question about setting the FILTER/GPIO4 pin for crystal/LVDS mode selection - should that pin be programmed as GPIO output (required level set by register write), or as input (required level set by external pull-up/pull-down)?
Thank you for your quick reply. I am going to repair the PWB and try it.RegardsMasayukiRegardsMaayuki
I will ask about the contents of your explanation.LVDS CLock
"Set the FILTER/GPIO4 pin (Pin 11) to logic 0. This will disable the crystal excitation circuitry."
There is no description in the data sheet AD7768 Rev.A Which literature is listed?regardsMasayuki
The next datasheet revision will be updated to reflect this information.