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AD7768/AD7768-4 FAQ - Clock Selection

The AD7768/AD7768-4 MCLK can be applied by using one of the three different options that are available to the user. The purpose of this document is to further explain these three options and how they are configured. The three options are: external CMOS clock, crystal oscillator or LVDS clock.

The initial power up of the AD7768/AD7768-4 uses an internal oscillator to set up the device. The clock control is then transferred to an external clock which is valid between 1.15 MHz and 32 MHz. (The maximum crystal frequency from the datasheet is 34 MHz) If the externally applied clock is not detected or an error occurs, then the Device Status register (Register 0x09) will log this error by setting the clock error bit to a one.

CMOS Clock

To select the CMOS clock option the following conditions must be met:

  • CLK_SEL (Pin 58) must be set to zero.
  • Connect XTAL1 (Pin 31) to DGND.
  • The CMOS clock is applied to pin 32.
  • The CMOS logic level in this case is between IOVDD and DGND.


In order to use an external crystal it is necessary to adhere to the following steps:

  • Channel four of the ADC must be enabled. This is because channel four is linked to the crystal excitation circuitry. Powering down this channel also powers down the crystal excitation circuitry.
  • The CLK_SEL pin must be set to a logic 1.
  • The crystal is applied between pins 31 and 32. Capacitance of approximately 20pF is required on each of these pins. This may vary depending on the crystal that is selected.
  • If the AD7768/AD7768-4 is in SPI control mode then the FILTER/GPIO4 pin (Pin 11) must be set to a logic one.

LVDS Clock

The LVDS clock option is available only in SPI control mode. The following steps must be carried out to enable LVDS clocking to be used:

  • Set the CLK_SEL pin to be a logic 1
  • Set the FILTER/GPIO4 pin (Pin 11) to logic 0. This will disable the crystal excitation circuitry.
  • Power up the AD7768 with no external clock applied. Initially it will run off the internal clock for SPI writes until all of the below steps have been carried out.
  • Enable this option by writing to the LVDS_Enable bit (Bit 3) in the Power_Mode register (Register 0x04)
  • Apply the LVDS signals on pins 31 and 32.

For further information please consult the product datasheet.

The AD7768/AD7768-4 evaluation boards allow the user the option to set the MCLK to one of the three options discussed above. The CMOS clock is enabled on these evaluation boards by default. For more information please see the products' evaluation board web page.

EVAL-AD7768 Evaluation Board | Analog Devices

  • FormerMember

    Hi Marekm,

    There are two scenarios here and both can be used to enable the LVDS clock option in SPI mode:

    1. Set GPIO4 to an output. Then writing to the LVDS bitfield in the POWER_CLOCK register will enable LVDS clock. 
    2. Set GPIO4 to an input. Then GPIO4 must be tied to logic 0 as described above.



  • Since the updated datasheet is not yet available, I have a question about setting the FILTER/GPIO4 pin for crystal/LVDS mode selection - should that pin be programmed as GPIO output (required level set by register write), or as input (required level set by external pull-up/pull-down)?

  • Hi NiallM

    Thank you for your quick reply. I am going to repair the PWB and try it.



  • Dear NiallM

    I will ask about the contents of your explanation.

    LVDS CLock

    "Set the FILTER/GPIO4 pin (Pin 11) to logic 0. This will disable the crystal excitation circuitry."

    There is no description in the data sheet AD7768 Rev.A Which literature is listed?

  • FormerMember
    FormerMember in reply to Mukai

    Hi Masayuki,

    The next datasheet revision will be updated to reflect this information.