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Interfacing the AD7768/AD7768-4 to a microcontroller

The AD7768/AD7768-4 outputs data as a master, meaning that the device continuously streams data and it is the user's task to read the data as it is output. Therefore the microcontroller that interfaces to the data output lines must be configured as a slave. (A separate interface needs to be configured if SPI control is required. If not, the AD7768/AD7768-4 can operate in pin control mode) 

The AD7768/AD7768-4 data interface has been tested by reading data using the Serial Audio Interface (SAI) on a microcontroller. For this example all 8 channels of AD7768 were output on DOUT0.

Connections Required

The connections required for the data interface on the AD7768 side are:

  • DRDY - this is the flag that signals new data is ready to be read.
  • DCLK - this is the data output clock.
  • DOUTx - this is the pin the data is output on. The AD7768 can output data on 1, 2 or 8 DOUT pins. The AD7768-4 can output data on 1 or 4 DOUT pins. DOUT0 was used for this test case.

The connections required to the microcontroller are:

  • FS (frame start). Used to signify a new conversion result is being output by the AD7768/AD7768-4. Connect this pin to DRDY on the AD7768/AD7768-4
  • SCLK (the interface clock) Used to clock the data into the microcontroller. Connect this pin to DCLK on the AD7768/AD7768-4. The master supplies the clock for the transaction, DCLK in this case. DCLK on the AD7768/AD7768-4 can be configured as a divided down version of the master clock (MCLK).
  • SD. (Serial data input) In the case where one DOUT is being used, this pin needs to be connected to DOUT0 on the AD7768/AD7768-4. 

Configuring the Interface

The microcontroller interface needs to be configured to accept the data output from the DOUT pins. For this example, all 8 channels of data are output on DOUT0 for the AD7768. Data is being read on the SAI interface which is configured as follows:

  • Configure the SAI as an asynchronous slave
  • Set the frame length to 256 bits. Data size is 32 bits. (32 bits x 8 channels = 256 bits total every DRDY)
  • Save data to 8 slots, each of 32 bit size

Configuring the AD7768

  • On the AD7768 configure FORMAT0 and FORMA1 pins to logic 1. This outputs all data on DOUT0.
  • Set the DCLK frequency to MCLK/1
  • The output data rate (ODR) can be set from the slowest possible rate up to 128kHz. If the max ODR of 256kHz is needed, two DOUT pins must be used to read all the data.

Note: On the AD7768-4 since there are only 4 channels the same constraint does not apply.

  • A related article is also available at the following link in the RAQ section of Analog Dialogue

  • FormerMember
    FormerMember in reply to dell-jin


    Without having looked specifically at the ADSP-SC570, I can confirm you can use the AD7768 with a SPORT interface



  • can the SPORT interface on ADI's adsp-sc570 DSP connect with AD7768? the SPORT is very similar with SAI. 

  • FormerMember


    In the example above the output data rate (ODR) was set to 128 kSPS. At this rate it is possible to output all 8 channels on one DOUT. Two DOUT lines will need to be used at the fastest rate of 256 kSPS.

    The ODR of 128 kSPS worked with the AD7768 as the SAI interface was configured as a slave. 

    I would recommend looking at an FPGA rather than a microcontroller for data rates of 256kSPS and 12 channels. At this rate it becomes a lot of data very quickly  and may be difficult to handle with multiple interfaces, processing of data etc.



  • Niall,

    I purchased the AD7768 dev kit and an STM32F446 Nucleo-144 board to experiment with interfacing to the AD7768, but I'm seeing some constraints on the interface of the AD7768 and the STM micro:

    On the AD7768:

     - You mention that all 8 channels can be output on DOUT0, but at the maximum MCLK of 32.768MHz and 256KS/s sampling rate, the maximum number of 32-bit channels that can be output is 4 - see the AD7768 datasheet, Rev A, pg 52 "With eight ADCs enabled, an MCLK rate of 32.768 MHz, an ODR of 256 kSPS, and two DOUTx channels, DCLK (minimum) is 256 kSPS × 4 channels per DOUTx × 32 bits = 32.768 MHz where DCLK = MCLK/1."  What sampling frequency were you using in your example?

    On the STM32:

     - From the STM32F446xC/E datasheet (which covers the STM32F446RE), DocID027107 Rev 6, it appears from Table 67 that the maximum SAI clock frequency (slave) is Fs x 128 (where Fs=192KHz) or 24.576MHz which would prevent a 4-channel TDM input from the AD7768 (which requires 32.768MHz).   What sampling frequency were you using in your example?

    My application:

    In my application, I'll be interfacing to 12 channels of ADC data (1 AD7768 and 1AD7768-4).  In order to sample at 256KS/s on all 12 channels, does this mean I'll need to output each ADC data channel separately (8 x DOUT won't work, 4 x DOUT won't work)?  If so, then I assume that the STM32F446RE will not work, as it has only 2 SAI peripherals with 2 channels inputs each (4 total).  Can you recommend a part that has 6 SAI peripherals?

    Please let me know.