AD7606C-16
Configuration: 4 SDO 4-Wire
|
No. of SCLK |
32 |
|
LSB CLK out |
31st SCLK rising edge |
|
1st FRSTDATA |
CSb falling edge to 16th SCLK falling edge |
|
2nd FRSTDATA |
No 2nd pulse |
We can see here in Figure 3., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.