AD7606C-16
Configuration: 1 SDO 4-Wire
|
No. of SCLK |
128 |
|
LSB CLK out |
127th SCLK rising edge |
|
1st FRSTDATA |
CSb falling edge to 16th SCLK falling edge |
|
2nd FRSTDATA |
128th SCLK falling edge to CSb rising edge |
We can see here in Figure 1. with the same response as the AD7606C-16, every first set of data that will be released for the AD7606C-16 triggers the FRTSDATA pin every time the next cycle or set of data will repeat again. The FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 128 pulses of SCLK. As we can see in the orange box, there is another FRSTDATA pulse from the incoming data set every time the next set of data will arrive specifically on the 128th SCLK falling edge till CSb rising edge.