AD7606C-18
Configuration: 2 SDO 4-Wire
|
No. of SCLK |
72 |
|
LSB CLK out |
71th SCLK rising edge |
|
1st FRSTDATA |
CSb falling edge to 18th SCLK falling edge |
|
2nd FRSTDATA |
72nd SCLK falling edge to CSb rising edge |
We can see here in Figure 2., every first set of data that will be released for the AD7606C-18 triggers the FRTSDATA pin every time the next cycle or set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 18th SCLK falling edge with 72 pulses of SCLK. As we can see in the orange box, there is another FRSTDATA pulse from the incoming data set every time the next set of data will arrive specifically on the 72nd SCLK falling edge till CSb rising edge.